📄 pciautoconfiglib.c
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pciAutoCfgCtl(pCookie, PCI_INT_ASSIGN_FUNC_SET, sysPciAutoconfigIntrAssign); /@ * PCI-to-PCI Bridge Pre- * and Post-enumeration init * routines @/ pciAutoCfgCtl(pCookie, PCI_BRIDGE_PRE_CONFIG_FUNC_SET, sysPciAutoconfigPreEnumBridgeInit); pciAutoCfgCtl(pCookie, PCI_BRIDGE_POST_CONFIG_FUNC_SET, sysPciAutoconfigPostEnumBridgeInit); /@ * Perform any needed PCI Host Bridge * Initialization that needs to be done * before pciAutoConfig is invoked here * utilizing the information in the * newly-populated sysParams structure. @/ pciAutoCfg (&sysParams); /@ * Perform any needed post-enumeration * PCI Host Bridge Initialization here. * Information about the actual configuration * from the scan and configuration passes * can be obtained using the assorted * PCI_*_GET commands to pciAutoCfgCtl(). @/ } /@ * Local BSP-Specific routines * supplied by BSP Developer @/STATUS sysPciAutoconfigInclude ( PCI_SYSTEM * pSys, /@ PCI_SYSTEM structure pointer @/ PCI_LOC * pLoc, /@ pointer to function in question @/ UINT devVend /@ deviceID/vendorID of device @/ ) { return OK; /@ Autoconfigure all devices @/ }UCHAR sysPciAutoconfigIntrAssign ( PCI_SYSTEM * pSys, /@ PCI_SYSTEM structure pointer @/ PCI_LOC * pLoc, /@ pointer to function in question @/ UCHAR pin /@ contents of PCI int pin register @/ ) { return (UCHAR)0xff; }void sysPciAutoconfigPreEnumBridgeInit ( PCI_SYSTEM * pSys, /@ PCI_SYSTEM structure pointer @/ PCI_LOC * pLoc, /@ pointer to function in question @/ UINT devVend /@ deviceID/vendorID of device @/ ) { return; }void sysPciAutoconfigPostEnumBridgeInit ( PCI_SYSTEM * pSys, /@ PCI_SYSTEM structure pointer @/ PCI_LOC * pLoc, /@ pointer to function in question @/ UINT devVend /@ deviceID/vendorID of device @/ ) { return; }.CECONFIGURATION SPACE PARAMETERSThe cache line size register specifies the cacheline size in longwords.This register is required when a device can generate a memory write andInvalidate bus cycle, or when a device provides cacheable memory to the system.Note that in the above example, the macro _CACHE_ALIGN_SIZE is utilized. Thismacro is implemented for all supported architectures and is located in the<architecture>.h file in .../target/h/arch/<architecture>. The value of themacro indicates the cache line size in bytes for the particular architecture.For example, the PowerPC architecture defines this macro to be 32, whilethe ARM 810 defines it to be 16. The PCI cache line size field andthe cacheSize element of the PCI_SYSTEM structure expect to see this quantityin longwords, so the byte value must be divided by 4.LIMITATIONSThe current version of the autoconfig facility does not support 64-bitprefetchable memory behind PCI-to-PCI bridges, but it does support32-bit prefetchable memory.The autoconfig code also depends upon the BSP Developer specifying resourcepools that do not conflict with any resources that are being used bystatically configured devices.INCLUDE FILES:pciAutoConfigLib.hSEE ALSO:.I "PCI Local Bus Specification, Revision 2.1, June 1, 1996".I "PCI Local Bus PCI to PCI Bridge Architecture Specification, Revision 1.0,April 5, 1994"INTERNAL: SIMPLE TEXT-BASED DEBUG SUPPORTNote that the macro PCI_AUTO_DEBUG may be defined, and the macroPCI_AUTO_DEBUG_MSG utilized. PCI_AUTO_DEBUG_MSG is identical to a functioncall to logMsg() in function in that it calls _func_logMsg() with thestring and six parameters passed to it. The macro also invokes taskDelayto allow the debug string to be sent with minimal interruption.Also note that the macro PCI_AUTO_DEBUG initializes a global variablepciAutoDebug to a non-zero value. Display of debug messages may be turnedon and off during runtime by manipulating this variable. If the variable isset to zero, messages will not be displayed.INTERNAL: ATTRIBUTESAttributes are reserved for use by the autoconfiguration routines. Thereis presently no user-level API at this time to access attributes for aparticular device. The BSP-specific device exclusion routine affectsthe attributes indirectly by specifying which devices are to be excludedfrom the scan and configuration process.Attributes are divided into device attributes and bridge attributes. The firstgroup below describes device attributes..IP "PCI_AUTO_ATTR_DEV_EXCLUDE" 32Specifies that a device is to be excluded from the automatic scanand configuration process.IP "PCI_AUTO_ATTR_DEV_DISPLAY" 32Specifies that a device is a display device.IP "PCI_AUTO_ATTR_DEV_PREFETCH" 32Specifies that a device has requested Prefetchable PCI memory.LPThe second group below describes Bridge attributes..IP "PCI_AUTO_ATTR_BUS_PREFETCH" 32Specifies that the bridge device supports Prefetchable Memory behind the bridge.IP "PCI_AUTO_ATTR_BUS_PCI" 32Specifies that the bridge device is a PCI-to-PCI bridge and implements a PCI bus.IP "PCI_AUTO_ATTR_BUS_HOST" 32Specifies that the bridge device is a PCI Host bridge and implements a PCI bus.IP "PCI_AUTO_ATTR_BUS_ISA" 32Specifies that the bridge device is an ISA bridge implements an ISA bus.IP "PCI_AUTO_ATTR_BUS_4GB_IO" 32Specifies that the bridge device supports 32-bit I/O Addressingbehind the bridge.LPINTERNAL: ATTRIBUTE INHERITANCEDevices that reside on a particular bus automatically inherit the attributesof the bridge (Host or PCI-to-PCI) that implements that bus. This allowsdevices to take advantage of the fact that, for example, a PCI-to-PCI bridgeimplements full 32-bit PCI I/O. Note that device attributes, such as theinclusion attribute, are not inherited.*//* includes */#include "vxWorks.h"#include "logLib.h"#include "taskLib.h"#include "string.h"#include "dllLib.h"#include "config.h"#include "errnoLib.h"#ifdef USE_PCI_SIMULATOR#include "stdio.h"#include "stdlib.h"#endif /* USE_PCI_SIMULATOR */#include "drv/pci/pciConfigLib.h"#include "drv/pci/pciAutoConfigLib.h"/* local defines */#define PCI_CMD_MASK 0xffff0000 /* mask to save status bits */#define NO_ALLOCATION 0xffffffff#define PCI_CONFIG_ABSENT_F 0xffff#define PCI_CONFIG_ABSENT_0 0x0000/* local configuration defines */#define PCI_AUTO_STATIC_LIST#undef PCI_AUTO_RECLAIM_LIST#ifndef PCI_AUTO_MAX_FUNCTIONS# define PCI_AUTO_MAX_FUNCTIONS 32#endif /* PCI_AUTO_MAX_FUNCTIONS */IMPORT FUNCPTR _func_logMsg;#define PCI_LOG_MSG(s, a, b, c, d, e, f) \ do { \ if (_func_logMsg != NULL) \ { \ (*_func_logMsg)(s, a, b, c, d, e, f); \ } \ else if ( ( pPciCfgOpts->pciConfigInit == TRUE ) && ( pPciCfgOpts->pciLogMsgFunc != NULL ) ) \ { \ (*(pPciCfgOpts->pciLogMsgFunc))(s,a,b,c,d,e,f); \ } \ } while (0)#define PCI_AUTO_DEBUG_MSG(s, a, b, c, d, e, f) \ do { \ if ( pciAutoDebug == TRUE ) \ { \ PCI_LOG_MSG (s, a, b, c, d, e, f); \ if ( taskIdCurrent != NULL ) \ taskDelay(10); \ } \ } while (0)/* typedefs */typedef struct pciAutoConfigOpts { /* copy of pSystem from pciAutoConfig() interface */ UINT pciMem32; /* 32 bit prefetchable memory location */ UINT pciMem32Size; /* 32 bit prefetchable memory size */ UINT pciMemIo32; /* 32 bit non-prefetchable memory location */ UINT pciMemIo32Size; /* 32 bit non-prefetchable memory size */ UINT pciIo32; /* 32 bit io location */ UINT pciIo32Size; /* 32 bit io size */ UINT pciIo16; /* 16 bit io location */ UINT pciIo16Size; /* 16 bit io size */ int maxBus; /* Highest subbus number */ int cacheSize; /* cache line size */ UINT maxLatency; /* max latency */ BOOL autoIntRouting; /* automatic routing strategy */ PCI_INCLUDE_FUNC includeRtn; PCI_INT_ASSIGN_FUNC intAssignRtn; PCI_BRIDGE_PRE_CONFIG_FUNC bridgePreConfigInit; PCI_BRIDGE_POST_CONFIG_FUNC bridgePostConfigInit; PCI_ROLL_CALL_FUNC pciRollcallRtn; /* new stuff not available in the obsolete PCI_SYSTEM structure */ BOOL pciConfigInit; /* internal use only */ /* Fast Back TO Back Enable */ BOOL pciFBBEnable; /* Enabled for system */ BOOL pciFBBActive; /* implemented all cards & turned on */ /* memory allocation */ UINT32 pciMemBusMinRes; /* minimum to reserve per bus */ UINT32 pciMemBusExtraRes; /* extra to reserve per bus */ UINT32 pciMemMax; /* maximum total to reserve */ UINT32 pciMem32Used; /* total 32-bit mem actually used */ UINT32 pciMemIo32Used; /* total 32-bit IOmem used */ UINT32 pciIo32Used; /* total 32-bit IO space used */ UINT32 pciIo16Used; /* total 16-bit IO space used */ PCI_MEM_BUS_EXTRA_FUNC pciMemBusExtraFunc; /* per bus, function to calculate */ /* misc functions */ PCI_LOGMSG_FUNC pciLogMsgFunc; /* safe logMsg() func */ PCI_MAX_LAT_FUNC pciMaxLatFunc; /* MAX_LAT calc each device */ void * pciMaxLatPArg; /* user-supplied arg */ /* PCI_AUTO_MAX_FUNCTIONS */ PCI_LOC * pFuncList; /* user-supplied space */ int numFuncListEntries; /* number of entries available */ BOOL minimizeResources; /* sort resource requirements */ } PCI_AUTO_CONFIG_OPTS;/* globals */#ifdef PCI_AUTO_DEBUGBOOL pciAutoDebug = TRUE;#elseBOOL pciAutoDebug = FALSE;#endifIMPORT int pciMaxBus;/* locals */LOCAL PCI_AUTO_CONFIG_OPTS pciAutoConfigOpts = { /* pSystem */ 0, /* pciMem32 */ 0, /* pciMem32Size */ 0, /* pciMemIo32 */ 0, /* pciMemIo32Size */ 0, /* pciIo32 */ 0, /* pciIo32Size */ 0, /* pciIo16 */ 0, /* pciIo16Size */ 0, /* maxBus */ 0, /* cacheSize */ 0, /* maxLatency */ FALSE, /* autoIntRouting */ NULL, /* includeRtn */ NULL, /* intAssignRtn */ NULL, /* bridgePreConfigInit */ NULL, /* bridgePostConfigInit */ NULL, /* pciRollCallRtn */ FALSE, /* is this structure valid? */ FALSE, /* Fast Back To Back enabled */ FALSE, /* Fast Back To Back active */ 0, /* mem 32-bit min to reserve */ 0, /* mem 32-bit extra to reserve */ 0, /* max total 32-bit memory */ 0, /* actual 32-bit mem used */ 0, /* actual 32-bit IOmem used */ 0, /* actual 32-bit IO space used */ 0, /* actual 16-bit IO space used */ NULL, /* per bus func to calculate extra mem */ NULL, /* logMsg() function */ NULL, /* function to calc MAX_LAT */ NULL, /* pArg for pciMaxLatFunc() */ NULL, /* pFuncList */ 0, /* number of entries available in pFuncList */ FALSE /* minimize resources */ };LOCAL PCI_AUTO_CONFIG_OPTS * pPciCfgOpts;#ifdef PCI_AUTO_STATIC_LISTLOCAL PCI_LOC pciAutoLocalFuncList[PCI_AUTO_MAX_FUNCTIONS];#endifLOCAL int lastPciListSize;LOCAL PCI_LOC *pLastPciList;LOCAL UCHAR pciAutoIntRoutingTable[4] = { (UCHAR) 0xff, (UCHAR) 0xff, (UCHAR) 0xff, (UCHAR) 0xff };/* forward declarations */LOCAL PCI_LOC * pciAutoListCreate ( PCI_AUTO_CONFIG_OPTS * pSystem, int *pListSize);LOCAL UINT pciAutoBusProbe ( PCI_AUTO_CONFIG_OPTS * pSystem, UINT priBus, UINT secBus, PCI_LOC* pPciLoc, PCI_LOC** ppPciList, int * pListSize);LOCAL UINT pciAutoDevProbe ( PCI_AUTO_CONFIG_OPTS * pSystem, UINT bus, UCHAR offset, UCHAR inheritAttrib, PCI_LOC **ppPciList, int * pListSize);LOCAL void pciAutoFuncConfigAll ( PCI_AUTO_CONFIG_OPTS * pSystem, PCI_LOC *pPciList, UINT nSize);LOCAL UCHAR pciAutoIntAssign ( PCI_AUTO_CONFIG_OPTS * pSystem, PCI_LOC * pFunc);LOCAL void pciAutoDevConfig ( PCI_AUTO_CONFIG_OPTS * pSystem, UINT bus, PCI_LOC **ppPciList, UINT *nSize);LOCAL void pciAutoFuncConfig ( PCI_AUTO_CONFIG_OPTS * pSystem, PCI_LOC * pPciFunc);LOCAL UINT pciAutoIoAlloc ( PCI_AUTO_CONFIG_OPTS * pPciSys, PCI_LOC *pPciFunc, UINT *pAlloc, UINT nSize);LOCAL UINT pciAutoMemAlloc ( PCI_AUTO_CONFIG_OPTS * pPciSys, PCI_LOC * pPciFunc, UINT * pAlloc, UINT size, UINT addrInfo);LOCAL void pciAutoBusConfig ( PCI_AUTO_CONFIG_OPTS * pSystem, PCI_LOC * pPciLoc, PCI_LOC **ppPciList, UINT *nSize);LOCAL STATUS pciAutoCfgFunc ( void *pCookie );LOCAL STATUS pciAutoConfigFBBEnable ( PCI_AUTO_CONFIG_OPTS * pOpts );LOCAL STATUS pciAutoConfigFBBDisable ( PCI_AUTO_CONFIG_OPTS * pOpts );LOCAL STATUS pciFBBFuncClear ( UINT bus, UINT device, UINT function, void *pArg );LOCAL STATUS pciFBBFuncSet ( UINT bus, UINT device, UINT function, void *pArg );LOCAL STATUS pciFBBFuncCheck ( UINT bus, UINT device, UINT function, void *pArg );LOCAL void pciAutoConfigCopyback ( PCI_AUTO_CONFIG_OPTS * pOpts, PCI_SYSTEM * pSystem);#ifdef USE_PCI_SIMULATORvoid pciAutoConfigListShow(PCI_LOC *pLoc, int num);#endif /* USE_PCI_SIMULATOR *//* subroutines */
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