sd_mem.h

sd卡的高速读写程序

/* Copyright 2002, ESS Technology, Inc.				*/
/* SCCSID @(#)sd_mem.h	1.8 11/01/03 */


#ifndef _SD_MEM_H_
#define _SD_MEM_H_

/******************************************************************/
/*                                                                */
/*      SD IO defined at "mem_dev.h"                              */
/*                                                                */
/******************************************************************/


/**************************************************************************
 * SD related constants and macros
 **************************************************************************/
#define SD_ACCEPTABLE_OCR	(0x007c<<16) /* 3.0 < Vdd < 3.5 */
#define SD_MAX_RETRIES		2

/* SD communication states */
#define SD_IDLE			0x0
#define HOST2SD_8CYCLES		0x1
#define HOST2SD_START		0x2
#define HOST2SD_CMD		0x3
#define HOST2SD_CRC7		0x4
#define HOST2SD_WAIT		0x5
#define HOST2SD_DATA1		0x6
#define HOST2SD_DATA4		0x7
#define HOST2SD_CRC16_DATA	0x8
#define HOST2SD_CHECK_BUSY	0x9
#define SD2HOST_NODATA		0xa
#define SD2HOST_DATA1		0xb
#define SD2HOST_DATA4		0xc
#define SD2HOST_CRC7_NODATA	0xd
#define SD2HOST_CRC16_DATA	0xe

/* SD Card internal states */
#define SD_STATE_IDLE		0x0
#define SD_STATE_READY		0x1
#define SD_STATE_IDENT		0x2
#define SD_STATE_STBY		0x3
#define SD_STATE_TRAN		0x4
#define SD_STATE_DATA		0x5
#define SD_STATE_RCV		0x6
#define SD_STATE_PRG		0x7
#define SD_STATE_DIS		0x8

/* SD command responses */
#define SD_NR	0x0	/* No response */
#define SD_R1	0x1
#define SD_R2	0x2
#define SD_R3	0x3
#define SD_R1b	0x4
#define SD_R6	0x6

/* SD responses for commands that drive data  */
#define SD_USE_DAT_RD	0x20 /* data line(s) for read */
#define SD_NR_RD	(SD_NR|SD_USE_DAT_RD)
#define SD_R1_RD	(SD_R1|SD_USE_DAT_RD)
#define SD_R1b_RD	(SD_R1b|SD_USE_DAT_RD)
#define SD_R2_RD	(SD_R2|SD_USE_DAT_RD)
#define SD_R3_RD	(SD_R3|SD_USE_DAT_RD)
#define SD_R6_RD	(SD_R6|SD_USE_DAT_RD)

#define SD_USE_DAT_WR	0x10 /* data line(s) for write */
#define SD_NR_WR	(SD_NR|SD_USE_DAT_WR)
#define SD_R1_WR	(SD_R1|SD_USE_DAT_WR)
#define SD_R1b_WR	(SD_R1b|SD_USE_DAT_WR)
#define SD_R2_WR	(SD_R2|SD_USE_DAT_WR)
#define SD_R3_WR	(SD_R3|SD_USE_DAT_WR)
#define SD_R6_WR	(SD_R6|SD_USE_DAT_WR)

/* SD command classes */
#define SD_CL0		0	/* basic */
#define SD_CL1		1	/* reserved */
#define SD_CL2		2	/* block read */
#define SD_CL3		3	/* reserved */
#define SD_CL4		4	/* block write */
#define SD_CL5		5	/* erase */
#define SD_CL6		6	/* write protection */
#define SD_CL7		7	/* lock card */
#define SD_CL8		8	/* application specific */
#define SD_CL9		9	/* reserved */
#define SD_CL10		10	/* reserved */
#define SD_CL11		11	/* reserved */
#define SD_CLX		12	/* No class defined */

/* Command format: 
 *	[start[47]|xmit[46]|index[45:40]|arg[39:8]|crc[7:1]|end[0]]
 */
#define SD_CMD_LENGTH		48	/* bits */
#define SD_CMD_INDEX_LENGTH	6	/* bits */
#define SD_CMD_ARG_LENGTH	32	/* bits */
#define SD_CMD_CRC_LENGTH	7	/* bits */
#define SD_CMD_START_BIT	0x0
#define SD_CMD_END_BIT		0x1
#define SD_CMD_HOST_XMIT_BIT	0x1

/* CMD INDEX */
#define SD_CMD_GO_IDLE_STATE		0	/* class 0 */
#define SD_CMD_MMC_SEND_OP_COND		1	/* class 0 */
#define SD_CMD_ALL_SEND_CID		2	/* class 0-R2 */
#define SD_CMD_SEND_REL_ADDR		3	/* class 0-R6 */
#define SD_CMD_SET_DSR			4	/* class 0 */
#define SD_CMD_RESERVED5		5	/* class 0 */
#define SD_CMD_RESERVED6		6	/* class 0 */
#define SD_CMD_SELECT_CARD		7	/* class 0-R1b */
#define SD_CMD_RESERVED8		8	/* class 0 */
#define SD_CMD_SEND_CSD			9	/* class 0-R2 */
#define SD_CMD_SEND_CID			10	/* class 0-R2 */
#define SD_CMD_RESERVED11		11	/* class 0 */
#define MMC_CMD_READ_UNTIL_STOP         11      /* class 1-R1 */
#define SD_CMD_STOP_TRANSMIT		12	/* class 0-R1b */
#define SD_CMD_SEND_STATUS		13	/* class 0-R1 */
#define SD_CMD_RESERVED14		14	/* class 0 */
#define SD_CMD_GO_INACTIVE_STATE	15	/* class 0 */
#define SD_CMD_SET_BLOCKLEN		16	/* class 2-R1 */
#define SD_CMD_READ_SINGLE_BLOCK	17	/* class 2-R1 */
#define SD_CMD_READ_MULTI_BLOCK		18	/* class 2-R1 */
#define SD_CMD_RESERVED19		19	/* class 2 */
#define SD_CMD_RESERVED20		20	/* class 2 */
#define SD_CMD_RESERVED21		21	/* class 2 */
#define SD_CMD_RESERVED22		22	/* class 2 */
#define SD_CMD_RESERVED23		23	/* class 2 */
#define MMC_CMD_SET_BLOCK_COUNT         23      /* class 2- R1 */
#define SD_CMD_WRITE_BLOCK		24	/* class 4-R1 */
#define SD_CMD_WRITE_MULTI_BLOCK	25	/* class 4-R1 */
#define SD_CMD_RESERVED26		26	/* class 4 */
#define SD_CMD_PROGRAM_CSD		27	/* class 4-R1 */
#define SD_CMD_SET_WRITE_PROT		28	/* class 6-R1b */
#define SD_CMD_CLR_WRITE_PROT		29	/* class 6-R1b */
#define SD_CMD_SEND_WRITE_PROT		30	/* class 6-R1 */
#define SD_CMD_RESERVED31		31	/* class 6 */
#define SD_CMD_ERASE_WR_BLK_START	32	/* class 5-R1 */
#define SD_CMD_ERASE_WR_BLK_END		33	/* class 5-R1 */
#define SD_CMD_RESERVED34		34	/* class 5 */
#define SD_CMD_RESERVED35		35	/* class 5 */
#define SD_CMD_RESERVED36		36	/* class 5 */
#define SD_CMD_RESERVED37		37	/* class 5 */
#define SD_CMD_ERASE			38	/* class 5-R1b */
#define SD_CMD_RESERVED39		39	/* class 5 */
#define SD_CMD_INVALID			40	/* class 5 */
#define SD_CMD_RESERVED41		41	/* class 5 */
#define SD_CMD_LOCK_UNLOCK		42	/* class 7-R1 */
#define SD_CMD_RESERVED43		43	/* class 7 */
#define SD_CMD_RESERVED44		44	/* class 7 */
#define SD_CMD_RESERVED45		45	/* class 7 */
#define SD_CMD_RESERVED46		46	/* class 7 */
#define SD_CMD_RESERVED47		47	/* class 7 */
#define SD_CMD_RESERVED48		48	/* class 7 */
#define SD_CMD_RESERVED49		49	/* class 7 */
#define SD_CMD_RESERVED50		50	/* class 7 */
#define SD_CMD_RESERVED51		51	/* class 7 */
#define SD_CMD_RESERVED52		52	/* class 7 */
#define SD_CMD_RESERVED53		53	/* class 7 */
#define SD_CMD_RESERVED54		54	/* class 7 */
#define SD_CMD_APP_CMD			55	/* class 8-R1 */
#define SD_CMD_GEN_CMD			56	/* class 8-R1 */
#define SD_CMD_RESERVED57		57	/* class 8 */
#define SD_CMD_RESERVED58		58	/* class 8 */
#define SD_CMD_RESERVED59		59	/* class 8 */
#define SD_CMD_RESERVED60		60	/* class 8 */
#define SD_CMD_RESERVED61		61	/* class 8 */
#define SD_CMD_RESERVED62		62	/* class 8 */
#define SD_CMD_RESERVED63		63	/* class 8 */
#define SD_CMD_EMPTY			SD_CMD_RESERVED63

/* ACMD INDEX (application specific..
 * must be preceded by SD_CMD_APP_CMD) 
 */
#define ACMD_MARKER			0x80
#define SD_ACMD_SET_BUS_WIDTH		(6|ACMD_MARKER) /* R1 */
#define SD_ACMD_SD_STATUS		(13|ACMD_MARKER) /* R1 */
#define SD_ACMD_RESERVED17		(17|ACMD_MARKER)
#define SD_ACMD_RESERVED18		(18|ACMD_MARKER)
#define SD_ACMD_RESERVED19		(19|ACMD_MARKER)
#define SD_ACMD_RESERVED20		(20|ACMD_MARKER)
#define SD_ACMD_RESERVED21		(21|ACMD_MARKER)
#define SD_ACMD_SEND_NUM_WR_BLOCKS	(22|ACMD_MARKER) /* R1 */
#define SD_ACMD_SET_WR_BLK_ERASE_CNT	(23|ACMD_MARKER) /* R1 */
#define SD_ACMD_RESERVED24		(24|ACMD_MARKER)
#define SD_ACMD_RESERVED25		(25|ACMD_MARKER)
#define SD_ACMD_RESERVED26		(26|ACMD_MARKER)
#define SD_ACMD_RESERVED38		(38|ACMD_MARKER)
#define SD_ACMD_RESERVED39		(39|ACMD_MARKER)
#define SD_ACMD_RESERVED40		(40|ACMD_MARKER)
#define SD_ACMD_SD_SEND_OP_COND		(41|ACMD_MARKER) /* R3 */
#define SD_ACMD_SET_CLR_CARD_DETECT	(42|ACMD_MARKER) /* R1 */
#define SD_ACMD_RESERVED43		(43|ACMD_MARKER)
#define SD_ACMD_RESERVED49		(49|ACMD_MARKER)
#define SD_ACMD_SEND_SCR		(51|ACMD_MARKER) /* R1 */

/* Command/Response delay info */
#define SD_NCR_MIN		2	/* clock cycles*/
#define SD_NCR_MAX		64	/* clock cycles*/
#define SD_NID_MIN		5	/* clock cycles*/
#define SD_NID_MAX		15	/* clock cycles*/
#define SD_NAC_MIN		2	/* clock cycles*/
#define SD_NRC_MIN		8	/* clock cycles*/
#define SD_NCC_MIN		8	/* clock cycles*/
#define SD_NWR_MIN		2	/* clock cycles*/

/* SD_card_info.type..*/
#define SD_IO		3 /* not yet */
#define SD_MEM		2
#define SD_MMC		1
#define SD_UNKNOWN	0

/* Response, R1 format (normal)..
 *     [start[47]|xmit[46]|index[45:40]|stat[39:8]|crc[7:1]|end[0]]
 */
#define SD_R1_LENGTH		48	/* bits */
#define SD_R1_INDEX_LENGTH	6	/* bits */
#define SD_R1_STATUS_LENGTH	32	/* bits */
#define SD_R1_CRC_LENGTH	7	/* bits */
#define SD_R1_START_BIT		0x0
#define SD_R1_END_BIT		0x1
#define SD_R1_CARD_XMIT_BIT	0x0

/* Response, R2 format (CID, CSD register)..
 *     [start[135]|xmit[134]|res[133:128]|reg[127:1]|end[0]]
 */
#define SD_R2_LENGTH		136	/* bits */
#define SD_R2_RESERVED_LENGTH	6	/* bits */
#define SD_R2_REG_LENGTH	127	/* bits */
#define SD_R2_START_BIT		0x0
#define SD_R2_END_BIT		0x1
#define SD_R2_CARD_XMIT_BIT	0x0

/* Response, R3 format (OCR register)..
 *     [start[47]|xmit[46]|res1[45:40]|reg[39:8]|res2[7:1]|end[0]]
 */
#define SD_R3_LENGTH		48	/* bits */