task_testmcbsp0.c

TI OMAP 1510上mcbsp的驱动程序

/*
 * dspapps/dsp/task_testB/hellotimer.c
 *
 * Example of DSP task which uses Timer Queue
 *
 * Copyright (C) 2002,2003 Nokia Corporation
 *
 * Written by Toshihiro Kobayashi <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * $Id: hellotimer.c
 * $Revision: 2.0
 * $Date: 2003/11/11
 *
 */
#include <std.h>
#include <sys.h>
#include <mem.h>
#include <type.h>
#include <timer.h>
#include <intr.h>

#include "mailbox.h"
#include "tokliBIOS.h"
//#include "dss.h"

#include "mcbsp55x.h"

//typedef unsigned int u16;

//McBsp Settings
#define MCBSP_PORT0   0

#define SPCR1_VAL   0
#define SPCR2_VAL   0

// set receive control reg values: receive data has single-phase
// frame with 16-bit word and 1-bit data delay
#define RCR1_VAL	(WORD_LENGTH_16<<5)
#define RCR2_VAL	((SINGLE_PHASE<<15) | DATA_DELAY1)

// set transmit control reg values: transmit data has single-phase
// frame with 16-bit word and 1-bit data delay
#define XCR1_VAL	(WORD_LENGTH_16<<5)
#define XCR2_VAL	((SINGLE_PHASE<<15) | DATA_DELAY1)

// set pin control reg values: transmit and receive frame-sync pulses are
// active high. Transmit data is clocked on rising edge of CLKX, while
// receive data is sampled on falling edge of CLKR.
#define PCR_VAL     ((FSYNC_POL_HIGH<<3)|(FSYNC_POL_HIGH<<2)|(CLKX_POL_RISING<<1)|(CLKR_POL_FALLING))


static Uns	tm0_rcv_wdsnd(struct dsptask *task, Uns data);
static Uns	tm0_callback(struct dsptask *task);
static Uns tm0_rcv_tctl(struct dsptask *task, Uns ctlcmd);

static void mcbsp0_start();

struct task_tm0 {
	struct dsptask	task_head;
	Int	cnt;
	Void	*t1q_id;
};

struct task_tm0 task_test_McBSP0 = {
	{
		TID_MAGIC,	// tid
		"testMcBSP0",	// name
		MBCMD_TTYP_BKDM | MBCMD_TTYP_ASND,
				// ttyp: active block snd, passive word rcv
		tm0_rcv_wdsnd,	// rcv_snd
		NULL,		// rcv_req
		tm0_rcv_tctl,	// rcv_tctl
		NULL		// tsk_attrs
	},
};


static Uns tm0_rcv_wdsnd(struct dsptask *task, Uns data)
{
	struct task_tm0	*task_tm0 = (struct task_tm0*)task;
	void	*qid;

	task_tm0->cnt = data;
	qid = register_tq_1s(task, tm0_callback);
	if(qid == MEM_ILLEGAL)
		return MBCMD_EID_NORES;
	task_tm0->t1q_id = qid;
	return 0;
}

#if 0
Int strcpy16to8(Char *d, Char *s)
{
	Int cnt = 0;

	for(; *s; s++, d++) {
		*d = *s;
		*d |= *++s << 8;
		cnt++;
		if(!*s)
			return cnt;
	}
	*d = '\0';
	return cnt;
}
#endif

static Uns tm0_callback(struct dsptask *task)
{
	struct task_tm0	*task_tm0 = (struct task_tm0*)task;
	Uns	bid;
	Int	cnt;
	Char	s[100];

	SYS_sprintf(s, "ht_callback(): task_ht->cnt = %d\n", task_tm0->cnt);
	dbg(task, s);
	bid = get_free_ipbuf(task);
	if(bid == MBCMD_BID_NULL)
		return MBCMD_EID_STVBUF;
	cnt = strcpy16to8((Char*)ipbuf_d[bid], "Hello from DSP!\n");
	bksnd(task, bid, cnt);
	task_tm0->cnt--;
	if(task_tm0->cnt == 0) {
		unregister_tq_1s(task, task_tm0->t1q_id);
	}
	return 0;
}


static Uns tm0_rcv_tctl(struct dsptask *task, Uns ctlcmd)
{
    struct task_tm0  *task_tm0 = (struct task_tm0*)task;
	Char	s[100];
	
    switch(ctlcmd) {
        case MBCMD_TCTL_TINIT:
			SYS_sprintf(s, "before DSS_init()\n");
			dbg(task, s);
			mcbsp0_start();
			SYS_sprintf(s, "after DSS_init()\n");
			dbg(task, s);			
            return 0;
        default:
            return MBCMD_EID_BADTCTL;
    }
}


void setup_serial_port()
{
	McBspConfig bsp;

    MCBSP_TX_RESET(MCBSP_PORT0);
    MCBSP_RX_RESET(MCBSP_PORT0);

    bsp.port   = MCBSP_PORT0;

	bsp.spcr1  = 0x00c0;
    bsp.spcr2  = 0x8000;
    bsp.rcr1   = 0x00c0;
    bsp.rcr2   = 0x0002;
    bsp.xcr1   = 0x00c0;
    bsp.xcr2   = 0x0002;

    bsp.srgr1  = 0x0101;
    bsp.srgr2  = 0x200f;

    bsp.mcr1   = 0x0000;
    bsp.mcr2   = 0x0000;

    bsp.pcr    = 0x0000;

#if 0
    bsp.rcera  = 0;
    bsp.xcera  = 0;
    bsp.rcerb  = 0;
    bsp.xcerb  = 0;
#endif
    
    bsp.rcerc  = 0x0000;
    bsp.xcerc  = 0x0000;
    bsp.rcerd  = 0x0000;
    bsp.xcerd  = 0;
    bsp.rcere  = 0;
    bsp.xcere  = 0;
    bsp.rcerf  = 0;
    bsp.xcerf  = 0;
    bsp.rcerg  = 0;
    bsp.xcerg  = 0;
    bsp.rcerh  = 0;
    bsp.xcerh  = 0;
    
	/****************************************************************/
	/* Set values of all control registers                          */
	/****************************************************************/
	mcbsp_init(&bsp);
	

	
}

#if 1
interrupt void _mcbsp0RvIsr(void)
{
	volatile u16 dummy;

    //increment codec count (48 kHz)
    //codec_count++;

    //read data from serial port
    dummy = DRR2(2);
    dummy = DRR1(2);
}

interrupt void _mcbsp0TxIsr(void)
{
	volatile u16 dummy;

    //increment codec count (48 kHz)
    //codec_count++;

    //read data from serial port
    dummy = DRR2(2);
    dummy = DRR1(2);
}

#endif


void mcbsp0_start()
{
	setup_serial_port();

    TIMER_HALT(TIMER_PORT1); //stop timer
	
	INTR_GLOBAL_DISABLE;

	// Disable interrupts
    IER0 &= ~(1<<RINT2);
    IER1 &= ~(1<<TINT1);
	
    // Clear pending interrupt flags (Note: Write 1 to clear)
    IFR0 |= (1<<RINT2);
    IFR1 |= (1<<TINT1);

	//setup interrupts
    hook_interrupt(RINT0_TRAP, _mcbsp0RvIsr);
    IER0 |= (1<<RINT0);
	
	//setup interrupts
    hook_interrupt(TINT0_TRAP, _mcbsp0TxIsr);
    IER0 |= (1<<TINT0);
    			
    MCBSP_ENABLE(MCBSP_PORT0, MCBSP_TX);
}