omap1510.h

TI OMAP 1510上mcbsp的驱动程序

/*
 * dspapps/dsp/tokliBIOS/omap1510.h
 *
 * OMAP1510 register definitions
 *
 * Copyright (C) 2002,2003 Nokia Corporation
 *
 * Written by Toshihiro Kobayashi <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * $Id: omap1510.h
 * $Revision: 2.0
 * $Date: 2003/11/11
 *
 */

#define inw(adr)	(*(ioport Uns*)adr)
#define outw(dat,adr)	(*(ioport Uns*)adr = dat)

#define DARAM_BASE	0x000000
#define DARAM_SIZE	0x008000
#define DARAM_TOP	0x008000
#define SARAM_BASE	0x008000
#define SARAM_SIZE	0x00c000
#define SARAM_TOP	0x014000

/*
 * ioport addresses (16bit word address)
 */
#define _ICR		0x0001
#define _ISR		0x0002

#define _ICR_BIT_EMIF_IDLE_DOMAIN	0x0020
#define _ICR_BIT_DPLL_IDLE_DOMAIN	0x0010
#define _ICR_BIT_PER_IDLE_DOMAIN	0x0008
#define _ICR_BIT_CACHE_IDLE_DOMAIN	0x0004
#define _ICR_BIT_DMA_IDLE_DOMAIN	0x0002
#define _ICR_BIT_CPU_IDLE_DOMAIN	0x0001

#define	_ICACHE_GCR	0x1400
#define	_ICACHE_NWCR	0x1403

#define _ICACHE_GCR_BIT_CUT_CLOCK		0x8000
#define _ICACHE_GCR_BIT_AUTO_GATING		0x4000
#define _ICACHE_GCR_BIT_FLUSH_LINE		0x1000
#define _ICACHE_GCR_BIT_GLOBAL_FLUSH		0x0800
#define _ICACHE_GCR_BIT_RAMSET_PRESENCE		0x0400
#define _ICACHE_GCR_BIT_WAY_PRESENCE		0x0200
#define _ICACHE_GCR_BIT_RAMSET_NUMBER_MASK	0x01e0
#define _ICACHE_GCR_BIT_RAMSET_NUMBER_1		0x0000
#define _ICACHE_GCR_BIT_RAMSET_NUMBER_2		0x0020
#define _ICACHE_GCR_BIT_WAY_NUMBER_MASK		0x0018
#define _ICACHE_GCR_BIT_WAY_NUMBER_1		0x0000
#define _ICACHE_GCR_BIT_WAY_NUMBER_2		0x0008
#define _ICACHE_GCR_BIT_STREAMING		0x0004
#define _ICACHE_GCR_BIT_RAM_FILL_MODE		0x0002
#define _ICACHE_GCR_BIT_GLOBAL_ENABLE		0x0001
#define _ICACHE_NWCR_BIT_WAY_SIZE_MASK		0x001c
#define _ICACHE_NWCR_BIT_WAY_SIZE_8K		0x000c
#define _ICACHE_NWCR_BIT_FLUSH			0x0002
#define _ICACHE_NWCR_BIT_ENABLE			0x0001

#define	_CNTL_TIMER1	0x2800
#define _LOAD_TIM_HI1	0x2802
#define _LOAD_TIM_LO1	0x2803

#define _CNTL_TIMERn_BIT_ST		0x0001
#define _CNTL_TIMERn_BIT_AR		0x0002
#define _CNTL_TIMERn_BIT_PTV(ptv)	((ptv)<<2)
#define _CNTL_TIMERn_BIT_CLOCK_ENABLE	0x0020
#define _CNTL_TIMERn_BIT_FREE		0x0040
#define _CNTL_TIMERn_BIT_SOFT		0x0080

#define _CNTL_TIMER	0x3400
#define _LOAD_TIM	0x3402
#define _READ_TIM	0x3402
#define _TIMER_MODE	0x3404

#define _CNTL_TIMER_BIT_FREE		0x0001
#define _CNTL_TIMER_BIT_ST		0x0080
#define _CNTL_TIMER_BIT_AR		0x0100
#define _CNTL_TIMER_BIT_PTV_MASK	0x0e00
#define _CNTL_TIMER_BIT_PTV(ptv)	((ptv)<<9)

#define _DSP_CKCTL	0x4000
#define _DSP_IDLECT1	0x4002
#define _DSP_IDLECT2	0x4004
#define _DSP_RSTCT2	0x400a
#define _DSP_SYSST	0x400c

#define _DSP_CKCTL_BIT_TIMXO		0x0100
#define _DSP_IDLECT1_BIT_IDLTIM_DSP	0x0100
#define _DSP_IDLECT1_BIT_IDLGPIO_DSP	0x0080
#define _DSP_IDLECT1_BIT_WKUP_MODE	0x0040
#define _DSP_IDLECT1_BIT_IDLDPLL_DSP	0x0020
#define _DSP_IDLECT1_BIT_IDLIF_DSP	0x0010
#define _DSP_IDLECT1_BIT_IDLPER_DSP	0x0004
#define _DSP_IDLECT1_BIT_IDLXORP_DSP	0x0002
#define _DSP_IDLECT1_BIT_IDLWDT_DSP	0x0001
#define _DSP_IDLECT2_BIT_EN_TIMCK	0x0020
#define _DSP_IDLECT2_BIT_EN_GPIOCK	0x0010
#define _DSP_IDLECT2_BIT_EN_PERCK	0x0004
#define _DSP_IDLECT2_BIT_EN_XORPCK	0x0002
#define _DSP_IDLECT2_BIT_EN_WDTCK	0x0001

#define _ARM2DSP1	0xf800
#define _ARM2DSP1b	0xf802
#define _DSP2ARM1	0xf804
#define _DSP2ARM1b	0xf806
#define _DSP2ARM1_Flag	0xf80e

/*
 * memory mapped registers
 */
#define _IER0	((Uns*)0x00)
#define _IFR0	((Uns*)0x01)
#define _ST1_55	((Uns*)0x03)
#define _ST3_55	((Uns*)0x04)
#define _IER1	((Uns*)0x45)
#define _IFR1	((Uns*)0x46)
#define _IVPD	((Uns*)0x49)
#define _IVPH	((Uns*)0x4a)

#define _IER0_BIT_MAILBOX1	(1<<5)
#define _IER0_BIT_WDGTIMER	(1<<13)
#define _ST1_55_BIT_INTM	0x0800
#define _ST3_55_BIT_CAFRZ	0x8000
#define _ST3_55_BIT_CAEN	0x4000
#define _ST3_55_BIT_CACLR	0x2000
#define _ST3_55_BIT_HOM_R	0x0200
#define _ST3_55_BIT_HOM_P	0x0100
#define _IER1_BIT_TIMER1	0x0080