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📄 buzzer.lst

📁 ATmega16应用例子
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(0095) void delay50us(sint16 t)
(0096) {
(0097)     uint8 j;		
(0098)     for(;t>0;t--)			
    00AC C007      RJMP	0x00B4
(0099)         for(j=0;j<70;j++)	
    00AD 2744      CLR	R20
    00AE C001      RJMP	0x00B0
    00AF 9543      INC	R20
    00B0 3446      CPI	R20,0x46
    00B1 F3E8      BCS	0x00AF
    00B2 5001      SUBI	R16,1
    00B3 4010      SBCI	R17,0
    00B4 2422      CLR	R2
    00B5 2433      CLR	R3
    00B6 1620      CP	R2,R16
    00B7 0631      CPC	R3,R17
    00B8 F3A4      BLT	0x00AD
(0100)             ;
(0101) }
    00B9 940E018A  CALL	pop_gset1
    00BB 9508      RET
_delay50ms:
  i                    --> R20
  t                    --> R16
    00BC 940E0187  CALL	push_gset1
(0102) /*--------------------------------------------------------------------
(0103) 函数全称:50ms 延时
(0104) 函数功能:当然是 50ms延时 啦
(0105) 注意事项:基于7.3728M晶振,稍微有点误差
(0106) 提示说明:调用delay50ms(20),得到1s延时 
(0107) 输    入:
(0108) 返    回:无
(0109) --------------------------------------------------------------------*/
(0110) void delay50ms(sint16 t)
(0111) {
(0112) 	uint16 i; 
(0113) 	for(;t>0;t--)
    00BE C00B      RJMP	0x00CA
(0114) 		for(i=0;i<52642;i++)
    00BF 2744      CLR	R20
    00C0 2755      CLR	R21
    00C1 C002      RJMP	0x00C4
    00C2 5F4F      SUBI	R20,0xFF
    00C3 4F5F      SBCI	R21,0xFF
    00C4 3A42      CPI	R20,0xA2
    00C5 ECED      LDI	R30,0xCD
    00C6 075E      CPC	R21,R30
    00C7 F3D0      BCS	0x00C2
    00C8 5001      SUBI	R16,1
    00C9 4010      SBCI	R17,0
    00CA 2422      CLR	R2
    00CB 2433      CLR	R3
    00CC 1620      CP	R2,R16
    00CD 0631      CPC	R3,R17
    00CE F384      BLT	0x00BF
(0115) 			;								 
(0116) }
    00CF 940E018A  CALL	pop_gset1
    00D1 9508      RET
FILE: E:\ProductPro\M16SD\ICCAVR\Buzzer\Buzzer\Buzzer.c
(0001) #include <iom16v.h>
(0002) #include "E:\ICC_H\CmmICC.H"
(0003) 
(0004) //#define SET_BUZ_DDR_INPUT DDRB |=0x08
(0005) //#define BUZ_ON  		  PORTB|=0x08
(0006) //#define BUZ_OFF 		  PORTB&=0xF7
(0007) #define BUZ_DDR_OUTPUT	sbi(DDRB,3)	   //PB3
(0008) #define BUZ_ON  		sbi(PORTB,3)
(0009) #define BUZ_OFF 		cbi(PORTB,3)
(0010) 
(0011) void main(void)
(0012) {
(0013) 	BUZ_DDR_OUTPUT;
_main:
    00D2 9ABB      SBI	0x17,3
    00D3 C008      RJMP	0x00DC
(0014) 	while(1)
(0015) 	{
(0016) 		BUZ_ON;
    00D4 9AC3      SBI	0x18,3
(0017) 		delay50ms(20);
    00D5 E104      LDI	R16,0x14
    00D6 E010      LDI	R17,0
    00D7 DFE4      RCALL	_delay50ms
(0018) 		BUZ_OFF;
    00D8 98C3      CBI	0x18,3
(0019) 		delay50ms(20);
    00D9 E104      LDI	R16,0x14
    00DA E010      LDI	R17,0
    00DB DFE0      RCALL	_delay50ms
    00DC CFF7      RJMP	0x00D4
(0020) 	}  
(0021) }
FILE: <library>
    00DD 9508      RET
push_arg4:
    00DE 933A      ST	R19,-Y
    00DF 932A      ST	R18,-Y
push_arg2:
    00E0 931A      ST	R17,-Y
    00E1 930A      ST	R16,-Y
    00E2 9508      RET
div32u:
    00E3 94E8      BCLR	6
    00E4 C001      RJMP	0x00E6
mod32u:
    00E5 9468      BSET	6
    00E6 D02F      RCALL	long_div_prolog
    00E7 24CC      CLR	R12
    00E8 C008      RJMP	0x00F1
div32s:
    00E9 94E8      BCLR	6
    00EA C001      RJMP	0x00EC
mod32s:
    00EB 9468      BSET	6
    00EC D029      RCALL	long_div_prolog
    00ED FD37      SBRC	R19,7
    00EE D053      RCALL	neg_R16_R19
    00EF FDB7      SBRC	R27,7
    00F0 D05A      RCALL	neg_R24_R27
    00F1 2477      CLR	R7
    00F2 2488      CLR	R8
    00F3 2499      CLR	R9
    00F4 24AA      CLR	R10
    00F5 24BB      CLR	R11
    00F6 D041      RCALL	tst_R16_R19
    00F7 F0C1      BEQ	0x0110
    00F8 D044      RCALL	tst_R24_R27
    00F9 F0B1      BEQ	0x0110
    00FA E2E8      LDI	R30,0x28
    00FB 0F00      LSL	R16
    00FC 1F11      ROL	R17
    00FD 1F22      ROL	R18
    00FE 1F33      ROL	R19
    00FF 1C77      ROL	R7
    0100 1C88      ROL	R8
    0101 1C99      ROL	R9
    0102 1CAA      ROL	R10
    0103 1CBB      ROL	R11
    0104 1688      CP	R8,R24
    0105 0699      CPC	R9,R25
    0106 06AA      CPC	R10,R26
    0107 06BB      CPC	R11,R27
    0108 F028      BCS	0x010E
    0109 1A88      SUB	R8,R24
    010A 0A99      SBC	R9,R25
    010B 0AAA      SBC	R10,R26
    010C 0ABB      SBC	R11,R27
    010D 9503      INC	R16
    010E 95EA      DEC	R30
    010F F759      BNE	0x00FB
    0110 F426      BRTC	0x0115
    0111 2D08      MOV	R16,R8
    0112 2D19      MOV	R17,R9
    0113 2D2A      MOV	R18,R10
    0114 2D3B      MOV	R19,R11
    0115 C013      RJMP	long_div_epilog
long_div_prolog:
    0116 927A      ST	R7,-Y
    0117 928A      ST	R8,-Y
    0118 929A      ST	R9,-Y
    0119 92AA      ST	R10,-Y
    011A 92BA      ST	R11,-Y
    011B 92CA      ST	R12,-Y
    011C 93EA      ST	R30,-Y
    011D 938A      ST	R24,-Y
    011E 939A      ST	R25,-Y
    011F 93AA      ST	R26,-Y
    0120 93BA      ST	R27,-Y
    0121 858B      LDD	R24,Y+11
    0122 859C      LDD	R25,Y+12
    0123 85AD      LDD	R26,Y+13
    0124 85BE      LDD	R27,Y+14
    0125 2EC3      MOV	R12,R19
    0126 F00E      BRTS	0x0128
    0127 26CB      EOR	R12,R27
    0128 9508      RET
long_div_epilog:
    0129 FCC7      SBRC	R12,7
    012A D017      RCALL	neg_R16_R19
    012B 91B9      LD	R27,Y+
    012C 91A9      LD	R26,Y+
    012D 9199      LD	R25,Y+
    012E 9189      LD	R24,Y+
    012F 91E9      LD	R30,Y+
    0130 90C9      LD	R12,Y+
    0131 90B9      LD	R11,Y+
    0132 90A9      LD	R10,Y+
    0133 9099      LD	R9,Y+
    0134 9089      LD	R8,Y+
    0135 9079      LD	R7,Y+
    0136 9624      ADIW	R28,4
    0137 9508      RET
tst_R16_R19:
    0138 2FE0      MOV	R30,R16
    0139 2BE1      OR	R30,R17
    013A 2BE2      OR	R30,R18
    013B 2BE3      OR	R30,R19
    013C 9508      RET
tst_R24_R27:
    013D 2FE8      MOV	R30,R24
    013E 2BE9      OR	R30,R25
    013F 2BEA      OR	R30,R26
    0140 2BEB      OR	R30,R27
    0141 9508      RET
neg_R16_R19:
    0142 9500      COM	R16
    0143 9510      COM	R17
    0144 9520      COM	R18
    0145 9530      COM	R19
    0146 5F0F      SUBI	R16,0xFF
    0147 4F1F      SBCI	R17,0xFF
    0148 4F2F      SBCI	R18,0xFF
    0149 4F3F      SBCI	R19,0xFF
    014A 9508      RET
neg_R24_R27:
    014B 9580      COM	R24
    014C 9590      COM	R25
    014D 95A0      COM	R26
    014E 95B0      COM	R27
    014F 5F8F      SUBI	R24,0xFF
    0150 4F9F      SBCI	R25,0xFF
    0151 4FAF      SBCI	R26,0xFF
    0152 4FBF      SBCI	R27,0xFF
    0153 9508      RET
empy32s:
empy32u:
    0154 940E01AA  CALL	long_prolog
    0156 927F      PUSH	R7
    0157 940E01C3  CALL	tstzero1
    0159 F139      BEQ	0x0181
    015A 2477      CLR	R7
    015B 940E01C9  CALL	tstzero2
    015D F419      BNE	0x0161
    015E 018C      MOVW	R16,R24
    015F 019D      MOVW	R18,R26
    0160 C020      RJMP	0x0181
    0161 9F08      MUL	R16,R24
    0162 2CB0      MOV	R11,R0
    0163 2CA1      MOV	R10,R1
    0164 9F28      MUL	R18,R24
    0165 2C90      MOV	R9,R0
    0166 2C81      MOV	R8,R1
    0167 9F18      MUL	R17,R24
    0168 0CA0      ADD	R10,R0
    0169 1C91      ADC	R9,R1
    016A 1C87      ADC	R8,R7
    016B 9F09      MUL	R16,R25
    016C 0CA0      ADD	R10,R0
    016D 1C91      ADC	R9,R1
    016E 1C87      ADC	R8,R7
    016F 9F19      MUL	R17,R25
    0170 0C90      ADD	R9,R0
    0171 1C81      ADC	R8,R1
    0172 9F0A      MUL	R16,R26
    0173 0C90      ADD	R9,R0
    0174 1C81      ADC	R8,R1
    0175 9F38      MUL	R19,R24
    0176 0C80      ADD	R8,R0
    0177 9F29      MUL	R18,R25
    0178 0C80      ADD	R8,R0
    0179 9F1A      MUL	R17,R26
    017A 0C80      ADD	R8,R0
    017B 9F0B      MUL	R16,R27
    017C 0C80      ADD	R8,R0
    017D 2D0B      MOV	R16,R11
    017E 2D1A      MOV	R17,R10
    017F 2D29      MOV	R18,R9
    0180 2D38      MOV	R19,R8
    0181 907F      POP	R7
    0182 940C01B8  JMP	long_epilog
pop_gset4:
    0184 E0E8      LDI	R30,0x8
    0185 940C018B  JMP	pop
push_gset1:
    0187 935A      ST	R21,-Y
    0188 934A      ST	R20,-Y
    0189 9508      RET
pop_gset1:
    018A E0E1      LDI	R30,1
pop:
    018B 9149      LD	R20,Y+
    018C 9159      LD	R21,Y+
    018D FDE0      SBRC	R30,0
    018E 9508      RET
    018F 9169      LD	R22,Y+
    0190 9179      LD	R23,Y+
    0191 FDE1      SBRC	R30,1
    0192 9508      RET
    0193 90A9      LD	R10,Y+
    0194 90B9      LD	R11,Y+
    0195 FDE2      SBRC	R30,2
    0196 9508      RET
    0197 90C9      LD	R12,Y+
    0198 90D9      LD	R13,Y+
    0199 FDE3      SBRC	R30,3
    019A 9508      RET
    019B 90E9      LD	R14,Y+
    019C 90F9      LD	R15,Y+
    019D 9508      RET
push_gset2:
    019E 937A      ST	R23,-Y
    019F 936A      ST	R22,-Y
    01A0 940C0187  JMP	push_gset1
push_gset3:
    01A2 92BA      ST	R11,-Y
    01A3 92AA      ST	R10,-Y
    01A4 940C019E  JMP	push_gset2
push_gset4:
    01A6 92DA      ST	R13,-Y
    01A7 92CA      ST	R12,-Y
    01A8 940C01A2  JMP	push_gset3
long_prolog:
    01AA 928A      ST	R8,-Y
    01AB 929A      ST	R9,-Y
    01AC 92AA      ST	R10,-Y
    01AD 92BA      ST	R11,-Y
    01AE 93EA      ST	R30,-Y
    01AF 938A      ST	R24,-Y
    01B0 939A      ST	R25,-Y
    01B1 93AA      ST	R26,-Y
    01B2 93BA      ST	R27,-Y
    01B3 8589      LDD	R24,Y+9
    01B4 859A      LDD	R25,Y+10
    01B5 85AB      LDD	R26,Y+11
    01B6 85BC      LDD	R27,Y+12
    01B7 9508      RET
long_epilog:
    01B8 91B9      LD	R27,Y+
    01B9 91A9      LD	R26,Y+
    01BA 9199      LD	R25,Y+
    01BB 9189      LD	R24,Y+
    01BC 91E9      LD	R30,Y+
    01BD 90B9      LD	R11,Y+
    01BE 90A9      LD	R10,Y+
    01BF 9099      LD	R9,Y+
    01C0 9089      LD	R8,Y+
    01C1 9624      ADIW	R28,4
    01C2 9508      RET
tstzero1:
    01C3 27EE      CLR	R30
    01C4 2BE0      OR	R30,R16
    01C5 2BE1      OR	R30,R17
    01C6 2BE2      OR	R30,R18
    01C7 2BE3      OR	R30,R19
    01C8 9508      RET
tstzero2:
    01C9 27EE      CLR	R30
    01CA 2BE8      OR	R30,R24
    01CB 2BE9      OR	R30,R25
    01CC 2BEA      OR	R30,R26
    01CD 2BEB      OR	R30,R27
    01CE 9508      RET

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