📄 pd3keyint.lst
字号:
00C1 C002 RJMP 0x00C4
00C2 5F4F SUBI R20,0xFF
00C3 4F5F SBCI R21,0xFF
00C4 3A42 CPI R20,0xA2
00C5 ECED LDI R30,0xCD
00C6 075E CPC R21,R30
00C7 F3D0 BCS 0x00C2
00C8 5001 SUBI R16,1
00C9 4010 SBCI R17,0
00CA 2422 CLR R2
00CB 2433 CLR R3
00CC 1620 CP R2,R16
00CD 0631 CPC R3,R17
00CE F384 BLT 0x00BF
(0117) ;
(0118) }
00CF 940E01A1 CALL pop_gset1
00D1 9508 RET
_int1_isr:
00D2 940E01E6 CALL push_lset
FILE: E:\ProductPro\M16SD\ICCAVR\PD3Key\PD3KeyInt\PD3KeyInt.C
(0001)
(0002) #include <iom16v.h>
(0003) #include "E:\ICC_H\CmmICC.H"
(0004)
(0005) #define DISP_DDR DDRB
(0006) #define DISP_PORT PORTB
(0007) #define IN_PD3 cbi(DDRD,3) //PD3
(0008) #define SET_PD3 sbi(PORTD,3)
(0009) #define GET_PD3 gbi(PIND,3)
(0010)
(0011) #pragma interrupt_handler int1_isr:3
(0012) void int1_isr(void)
(0013) {
(0014) GICR &= 0b01111111; // disable int1 interrupt
00D4 B78B IN R24,0x3B
00D5 778F ANDI R24,0x7F
00D6 BF8B OUT 0x3B,R24
(0015) DISP_PORT++;
00D7 B388 IN R24,0x18
00D8 5F8F SUBI R24,0xFF
00D9 BB88 OUT 0x18,R24
(0016) delay50ms(4);
00DA E004 LDI R16,4
00DB E010 LDI R17,0
00DC DFDF RCALL _delay50ms
(0017) GICR |= 0b10000000; // enable int1 interrupt
00DD B78B IN R24,0x3B
00DE 6880 ORI R24,0x80
00DF BF8B OUT 0x3B,R24
(0018) }
00E0 940E01FD CALL pop_lset
00E2 9518 RETI
(0019)
(0020) void int1_init()
(0021) {
(0022) IN_PD3; // set PD3/INT1 as input
_int1_init:
00E3 988B CBI 0x11,3
(0023) SET_PD3; // set PD3/INT1 output high level,avoid triggering
00E4 9A93 SBI 0x12,3
(0024) MCUCR |= 0b11110011; // set PD3/INT1 as low level active
00E5 B785 IN R24,0x35
00E6 6F83 ORI R24,0xF3
00E7 BF85 OUT 0x35,R24
(0025) GICR |= 0b10000000; // enable global interrupt
00E8 B78B IN R24,0x3B
00E9 6880 ORI R24,0x80
00EA BF8B OUT 0x3B,R24
(0026) SEI(); // enable external interrupt
00EB 9478 BSET 7
(0027) }
00EC 9508 RET
(0028)
(0029) void main(void)
(0030) {
(0031) DISP_DDR = 0xFF;
_main:
00ED EF8F LDI R24,0xFF
00EE BB87 OUT 0x17,R24
(0032) DISP_PORT = 0x00;
00EF 2422 CLR R2
00F0 BA28 OUT 0x18,R2
(0033) int1_init();
00F1 DFF1 RCALL _int1_init
(0034) asm("sleep"); // set mcu as sleep modle
00F2 9588 SLEEP
(0035) while(1);
00F3 CFFF RJMP 0x00F3
(0036) }
FILE: <library>
00F4 9508 RET
push_arg4:
00F5 933A ST R19,-Y
00F6 932A ST R18,-Y
push_arg2:
00F7 931A ST R17,-Y
00F8 930A ST R16,-Y
00F9 9508 RET
div32u:
00FA 94E8 BCLR 6
00FB C001 RJMP 0x00FD
mod32u:
00FC 9468 BSET 6
00FD D02F RCALL long_div_prolog
00FE 24CC CLR R12
00FF C008 RJMP 0x0108
div32s:
0100 94E8 BCLR 6
0101 C001 RJMP 0x0103
mod32s:
0102 9468 BSET 6
0103 D029 RCALL long_div_prolog
0104 FD37 SBRC R19,7
0105 D053 RCALL neg_R16_R19
0106 FDB7 SBRC R27,7
0107 D05A RCALL neg_R24_R27
0108 2477 CLR R7
0109 2488 CLR R8
010A 2499 CLR R9
010B 24AA CLR R10
010C 24BB CLR R11
010D D041 RCALL tst_R16_R19
010E F0C1 BEQ 0x0127
010F D044 RCALL tst_R24_R27
0110 F0B1 BEQ 0x0127
0111 E2E8 LDI R30,0x28
0112 0F00 LSL R16
0113 1F11 ROL R17
0114 1F22 ROL R18
0115 1F33 ROL R19
0116 1C77 ROL R7
0117 1C88 ROL R8
0118 1C99 ROL R9
0119 1CAA ROL R10
011A 1CBB ROL R11
011B 1688 CP R8,R24
011C 0699 CPC R9,R25
011D 06AA CPC R10,R26
011E 06BB CPC R11,R27
011F F028 BCS 0x0125
0120 1A88 SUB R8,R24
0121 0A99 SBC R9,R25
0122 0AAA SBC R10,R26
0123 0ABB SBC R11,R27
0124 9503 INC R16
0125 95EA DEC R30
0126 F759 BNE 0x0112
0127 F426 BRTC 0x012C
0128 2D08 MOV R16,R8
0129 2D19 MOV R17,R9
012A 2D2A MOV R18,R10
012B 2D3B MOV R19,R11
012C C013 RJMP long_div_epilog
long_div_prolog:
012D 927A ST R7,-Y
012E 928A ST R8,-Y
012F 929A ST R9,-Y
0130 92AA ST R10,-Y
0131 92BA ST R11,-Y
0132 92CA ST R12,-Y
0133 93EA ST R30,-Y
0134 938A ST R24,-Y
0135 939A ST R25,-Y
0136 93AA ST R26,-Y
0137 93BA ST R27,-Y
0138 858B LDD R24,Y+11
0139 859C LDD R25,Y+12
013A 85AD LDD R26,Y+13
013B 85BE LDD R27,Y+14
013C 2EC3 MOV R12,R19
013D F00E BRTS 0x013F
013E 26CB EOR R12,R27
013F 9508 RET
long_div_epilog:
0140 FCC7 SBRC R12,7
0141 D017 RCALL neg_R16_R19
0142 91B9 LD R27,Y+
0143 91A9 LD R26,Y+
0144 9199 LD R25,Y+
0145 9189 LD R24,Y+
0146 91E9 LD R30,Y+
0147 90C9 LD R12,Y+
0148 90B9 LD R11,Y+
0149 90A9 LD R10,Y+
014A 9099 LD R9,Y+
014B 9089 LD R8,Y+
014C 9079 LD R7,Y+
014D 9624 ADIW R28,4
014E 9508 RET
tst_R16_R19:
014F 2FE0 MOV R30,R16
0150 2BE1 OR R30,R17
0151 2BE2 OR R30,R18
0152 2BE3 OR R30,R19
0153 9508 RET
tst_R24_R27:
0154 2FE8 MOV R30,R24
0155 2BE9 OR R30,R25
0156 2BEA OR R30,R26
0157 2BEB OR R30,R27
0158 9508 RET
neg_R16_R19:
0159 9500 COM R16
015A 9510 COM R17
015B 9520 COM R18
015C 9530 COM R19
015D 5F0F SUBI R16,0xFF
015E 4F1F SBCI R17,0xFF
015F 4F2F SBCI R18,0xFF
0160 4F3F SBCI R19,0xFF
0161 9508 RET
neg_R24_R27:
0162 9580 COM R24
0163 9590 COM R25
0164 95A0 COM R26
0165 95B0 COM R27
0166 5F8F SUBI R24,0xFF
0167 4F9F SBCI R25,0xFF
0168 4FAF SBCI R26,0xFF
0169 4FBF SBCI R27,0xFF
016A 9508 RET
empy32u:
empy32s:
016B 940E01C1 CALL long_prolog
016D 927F PUSH R7
016E 940E01DA CALL tstzero1
0170 F139 BEQ 0x0198
0171 2477 CLR R7
0172 940E01E0 CALL tstzero2
0174 F419 BNE 0x0178
0175 018C MOVW R16,R24
0176 019D MOVW R18,R26
0177 C020 RJMP 0x0198
0178 9F08 MUL R16,R24
0179 2CB0 MOV R11,R0
017A 2CA1 MOV R10,R1
017B 9F28 MUL R18,R24
017C 2C90 MOV R9,R0
017D 2C81 MOV R8,R1
017E 9F18 MUL R17,R24
017F 0CA0 ADD R10,R0
0180 1C91 ADC R9,R1
0181 1C87 ADC R8,R7
0182 9F09 MUL R16,R25
0183 0CA0 ADD R10,R0
0184 1C91 ADC R9,R1
0185 1C87 ADC R8,R7
0186 9F19 MUL R17,R25
0187 0C90 ADD R9,R0
0188 1C81 ADC R8,R1
0189 9F0A MUL R16,R26
018A 0C90 ADD R9,R0
018B 1C81 ADC R8,R1
018C 9F38 MUL R19,R24
018D 0C80 ADD R8,R0
018E 9F29 MUL R18,R25
018F 0C80 ADD R8,R0
0190 9F1A MUL R17,R26
0191 0C80 ADD R8,R0
0192 9F0B MUL R16,R27
0193 0C80 ADD R8,R0
0194 2D0B MOV R16,R11
0195 2D1A MOV R17,R10
0196 2D29 MOV R18,R9
0197 2D38 MOV R19,R8
0198 907F POP R7
0199 940C01CF JMP long_epilog
pop_gset4:
019B E0E8 LDI R30,0x8
019C 940C01A2 JMP pop
push_gset1:
019E 935A ST R21,-Y
019F 934A ST R20,-Y
01A0 9508 RET
pop_gset1:
01A1 E0E1 LDI R30,1
pop:
01A2 9149 LD R20,Y+
01A3 9159 LD R21,Y+
01A4 FDE0 SBRC R30,0
01A5 9508 RET
01A6 9169 LD R22,Y+
01A7 9179 LD R23,Y+
01A8 FDE1 SBRC R30,1
01A9 9508 RET
01AA 90A9 LD R10,Y+
01AB 90B9 LD R11,Y+
01AC FDE2 SBRC R30,2
01AD 9508 RET
01AE 90C9 LD R12,Y+
01AF 90D9 LD R13,Y+
01B0 FDE3 SBRC R30,3
01B1 9508 RET
01B2 90E9 LD R14,Y+
01B3 90F9 LD R15,Y+
01B4 9508 RET
push_gset2:
01B5 937A ST R23,-Y
01B6 936A ST R22,-Y
01B7 940C019E JMP push_gset1
push_gset3:
01B9 92BA ST R11,-Y
01BA 92AA ST R10,-Y
01BB 940C01B5 JMP push_gset2
push_gset4:
01BD 92DA ST R13,-Y
01BE 92CA ST R12,-Y
01BF 940C01B9 JMP push_gset3
long_prolog:
01C1 928A ST R8,-Y
01C2 929A ST R9,-Y
01C3 92AA ST R10,-Y
01C4 92BA ST R11,-Y
01C5 93EA ST R30,-Y
01C6 938A ST R24,-Y
01C7 939A ST R25,-Y
01C8 93AA ST R26,-Y
01C9 93BA ST R27,-Y
01CA 8589 LDD R24,Y+9
01CB 859A LDD R25,Y+10
01CC 85AB LDD R26,Y+11
01CD 85BC LDD R27,Y+12
01CE 9508 RET
long_epilog:
01CF 91B9 LD R27,Y+
01D0 91A9 LD R26,Y+
01D1 9199 LD R25,Y+
01D2 9189 LD R24,Y+
01D3 91E9 LD R30,Y+
01D4 90B9 LD R11,Y+
01D5 90A9 LD R10,Y+
01D6 9099 LD R9,Y+
01D7 9089 LD R8,Y+
01D8 9624 ADIW R28,4
01D9 9508 RET
tstzero1:
01DA 27EE CLR R30
01DB 2BE0 OR R30,R16
01DC 2BE1 OR R30,R17
01DD 2BE2 OR R30,R18
01DE 2BE3 OR R30,R19
01DF 9508 RET
tstzero2:
01E0 27EE CLR R30
01E1 2BE8 OR R30,R24
01E2 2BE9 OR R30,R25
01E3 2BEA OR R30,R26
01E4 2BEB OR R30,R27
01E5 9508 RET
push_lset:
01E6 93FA ST R31,-Y
01E7 93EA ST R30,-Y
01E8 93BA ST R27,-Y
01E9 93AA ST R26,-Y
01EA 939A ST R25,-Y
01EB 938A ST R24,-Y
01EC 933A ST R19,-Y
01ED 932A ST R18,-Y
01EE 931A ST R17,-Y
01EF 930A ST R16,-Y
01F0 929A ST R9,-Y
01F1 928A ST R8,-Y
01F2 927A ST R7,-Y
01F3 926A ST R6,-Y
01F4 925A ST R5,-Y
01F5 924A ST R4,-Y
01F6 923A ST R3,-Y
01F7 922A ST R2,-Y
01F8 921A ST R1,-Y
01F9 920A ST R0,-Y
01FA B60F IN R0,0x3F
01FB 920A ST R0,-Y
01FC 9508 RET
pop_lset:
01FD 9009 LD R0,Y+
01FE BE0F OUT 0x3F,R0
01FF 9009 LD R0,Y+
0200 9019 LD R1,Y+
0201 9029 LD R2,Y+
0202 9039 LD R3,Y+
0203 9049 LD R4,Y+
0204 9059 LD R5,Y+
0205 9069 LD R6,Y+
0206 9079 LD R7,Y+
0207 9089 LD R8,Y+
0208 9099 LD R9,Y+
0209 9109 LD R16,Y+
020A 9119 LD R17,Y+
020B 9129 LD R18,Y+
020C 9139 LD R19,Y+
020D 9189 LD R24,Y+
020E 9199 LD R25,Y+
020F 91A9 LD R26,Y+
0210 91B9 LD R27,Y+
0211 91E9 LD R30,Y+
0212 91F9 LD R31,Y+
0213 9508 RET
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