📄 74ls164.lst
字号:
(0015)
(0016) 说 明: 若用于商业用途，请保留此段文字或注明代码来源
(0017)
(0018) 深 圳 微 雪 电 子 保 留 所 有 的 版 权
(0019) *********************************************************************/
(0020)
(0021) /*01010101010101010101010101010101010101010101010101010101010101010101
(0022) ----------------------------------------------------------------------
(0023) 版本更新记录：
(0024)
(0025) ----------------------------------------------------------------------
(0026) 实验内容：
(0027) 使用PB口的LED指示灯查看MCU自己从串口发送的数据。
(0028) ----------------------------------------------------------------------
(0029) 硬件连接：
(0030) 接口说明： SeialBoard(164PrlPort) M16SD
(0031) Q0 --------- PB0
(0032) Q1 --------- PB1
(0033) Q2 --------- PB2
(0034) Q3 --------- PB3
(0035) Q4 --------- PB4
(0036) Q5 --------- PB5
(0037) Q6 --------- PB6
(0038) Q7 --------- PB7
(0039) SeialBoard(164SrlPort) M16SD
(0040) VCC --------- VCC
(0041) GND --------- GND
(0042) TXD --------- RXD
(0043) RXD --------- TXD
(0044) ----------------------------------------------------------------------
(0045) 注意事项：
(0046) 详见M16SD说明书
(0047) ----------------------------------------------------------------------
(0048) 10101010101010101010101010101010101010101010101010101010101010101010*/
(0049)
(0050) #include <iom16v.h>
(0051) #include "D:\ICC_H\CmmICC.H"
(0052)
(0053) #define DISP_PORT PORTB
(0054) #define DISP_DDR DDRB
(0055)
(0056) #define OUT_RXD sbi(DDRD,0) //PD0 数据口
(0057) #define SET_RXD sbi(PORTD,0)
(0058) #define CLR_RXD cbi(PORTD,0)
(0059) #define OUT_TXD sbi(DDRD,1) //PD1 脉冲口
(0060) #define SET_TXD sbi(PORTD,1)
(0061) #define CLR_TXD cbi(PORTD,1)
(0062)
(0063)
(0064) //#define data7 (bool)operData&0x80
(0065)
(0066) /*--------------------------------------------------------------------
(0067) 函数名称：
(0068) 函数功能：
(0069) 注意事项：
(0070) 提示说明：
(0071) 输 入：
(0072) 返 回：
(0073) --------------------------------------------------------------------*/
(0074) void output(uint8 dat)
(0075) {
(0076) uint8 i;
(0077)
(0078) for(i=0;i<8;i++)
01FC 2744 CLR R20
01FD C009 RJMP 0x0207
(0079) {
(0080) SET_TXD;
01FE 9A91 SBI 0x12,1
(0081) if((bool)dat&0x01)
01FF FF00 SBRS R16,0
0200 C002 RJMP 0x0203
(0082) SET_RXD;
0201 9A90 SBI 0x12,0
0202 C001 RJMP 0x0204
(0083) else
(0084) CLR_RXD;
0203 9890 CBI 0x12,0
(0085) CLR_TXD;
0204 9891 CBI 0x12,1
(0086) dat = dat>>1;
0205 9506 LSR R16
0206 9543 INC R20
0207 3048 CPI R20,0x8
0208 F3A8 BCS 0x01FE
0209 940E02CA CALL pop_gset1
020B 9508 RET
(0087) }
(0088) }
(0089) /*--------------------------------------------------------------------
(0090) 函数名称：
(0091) 函数功能：
(0092) 注意事项：
(0093) 提示说明：
(0094) 输 入：
(0095) 返 回：
(0096) --------------------------------------------------------------------*/
(0097) void main()
(0098) {
(0099) uint8 dat=0X55; //改变dat，观察数据变化
_main:
dat --> R20
020C E545 LDI R20,0x55
(0100)
(0101) OUT_RXD;
020D 9A88 SBI 0x11,0
(0102) OUT_TXD;
020E 9A89 SBI 0x11,1
(0103) output(dat);
020F 2F04 MOV R16,R20
0210 DFE9 RCALL _output
(0104) while(1);
FILE: <library>
0211 CFFF RJMP 0x0211
0212 9508 RET
push_arg4:
0213 933A ST R19,-Y
0214 932A ST R18,-Y
push_arg2:
0215 931A ST R17,-Y
0216 930A ST R16,-Y
0217 9508 RET
div32u:
0218 94E8 BCLR 6
0219 C001 RJMP 0x021B
mod32u:
021A 9468 BSET 6
021B D02F RCALL long_div_prolog
021C 24CC CLR R12
021D C008 RJMP 0x0226
div32s:
021E 94E8 BCLR 6
021F C001 RJMP 0x0221
mod32s:
0220 9468 BSET 6
0221 D029 RCALL long_div_prolog
0222 FD37 SBRC R19,7
0223 D053 RCALL neg_R16_R19
0224 FDB7 SBRC R27,7
0225 D05A RCALL neg_R24_R27
0226 2477 CLR R7
0227 2488 CLR R8
0228 2499 CLR R9
0229 24AA CLR R10
022A 24BB CLR R11
022B D041 RCALL tst_R16_R19
022C F0C1 BEQ 0x0245
022D D044 RCALL tst_R24_R27
022E F0B1 BEQ 0x0245
022F E2E8 LDI R30,0x28
0230 0F00 LSL R16
0231 1F11 ROL R17
0232 1F22 ROL R18
0233 1F33 ROL R19
0234 1C77 ROL R7
0235 1C88 ROL R8
0236 1C99 ROL R9
0237 1CAA ROL R10
0238 1CBB ROL R11
0239 1688 CP R8,R24
023A 0699 CPC R9,R25
023B 06AA CPC R10,R26
023C 06BB CPC R11,R27
023D F028 BCS 0x0243
023E 1A88 SUB R8,R24
023F 0A99 SBC R9,R25
0240 0AAA SBC R10,R26
0241 0ABB SBC R11,R27
0242 9503 INC R16
0243 95EA DEC R30
0244 F759 BNE 0x0230
0245 F426 BRTC 0x024A
0246 2D08 MOV R16,R8
0247 2D19 MOV R17,R9
0248 2D2A MOV R18,R10
0249 2D3B MOV R19,R11
024A C013 RJMP long_div_epilog
long_div_prolog:
024B 927A ST R7,-Y
024C 928A ST R8,-Y
024D 929A ST R9,-Y
024E 92AA ST R10,-Y
024F 92BA ST R11,-Y
0250 92CA ST R12,-Y
0251 93EA ST R30,-Y
0252 938A ST R24,-Y
0253 939A ST R25,-Y
0254 93AA ST R26,-Y
0255 93BA ST R27,-Y
0256 858B LDD R24,Y+11
0257 859C LDD R25,Y+12
0258 85AD LDD R26,Y+13
0259 85BE LDD R27,Y+14
025A 2EC3 MOV R12,R19
025B F00E BRTS 0x025D
025C 26CB EOR R12,R27
025D 9508 RET
long_div_epilog:
025E FCC7 SBRC R12,7
025F D017 RCALL neg_R16_R19
0260 91B9 LD R27,Y+
0261 91A9 LD R26,Y+
0262 9199 LD R25,Y+
0263 9189 LD R24,Y+
0264 91E9 LD R30,Y+
0265 90C9 LD R12,Y+
0266 90B9 LD R11,Y+
0267 90A9 LD R10,Y+
0268 9099 LD R9,Y+
0269 9089 LD R8,Y+
026A 9079 LD R7,Y+
026B 9624 ADIW R28,4
026C 9508 RET
tst_R16_R19:
026D 2FE0 MOV R30,R16
026E 2BE1 OR R30,R17
026F 2BE2 OR R30,R18
0270 2BE3 OR R30,R19
0271 9508 RET
tst_R24_R27:
0272 2FE8 MOV R30,R24
0273 2BE9 OR R30,R25
0274 2BEA OR R30,R26
0275 2BEB OR R30,R27
0276 9508 RET
neg_R16_R19:
0277 9500 COM R16
0278 9510 COM R17
0279 9520 COM R18
027A 9530 COM R19
027B 5F0F SUBI R16,0xFF
027C 4F1F SBCI R17,0xFF
027D 4F2F SBCI R18,0xFF
027E 4F3F SBCI R19,0xFF
027F 9508 RET
neg_R24_R27:
0280 9580 COM R24
0281 9590 COM R25
0282 95A0 COM R26
0283 95B0 COM R27
0284 5F8F SUBI R24,0xFF
0285 4F9F SBCI R25,0xFF
0286 4FAF SBCI R26,0xFF
0287 4FBF SBCI R27,0xFF
0288 9508 RET
empy32s:
empy32u:
0289 940E02DE CALL long_prolog
028B 927F PUSH R7
028C 940E02F7 CALL tstzero1
028E F139 BEQ 0x02B6
028F 2477 CLR R7
0290 940E02FD CALL tstzero2
0292 F419 BNE 0x0296
0293 018C MOVW R16,R24
0294 019D MOVW R18,R26
0295 C020 RJMP 0x02B6
0296 9F08 MUL R16,R24
0297 2CB0 MOV R11,R0
0298 2CA1 MOV R10,R1
0299 9F28 MUL R18,R24
029A 2C90 MOV R9,R0
029B 2C81 MOV R8,R1
029C 9F18 MUL R17,R24
029D 0CA0 ADD R10,R0
029E 1C91 ADC R9,R1
029F 1C87 ADC R8,R7
02A0 9F09 MUL R16,R25
02A1 0CA0 ADD R10,R0
02A2 1C91 ADC R9,R1
02A3 1C87 ADC R8,R7
02A4 9F19 MUL R17,R25
02A5 0C90 ADD R9,R0
02A6 1C81 ADC R8,R1
02A7 9F0A MUL R16,R26
02A8 0C90 ADD R9,R0
02A9 1C81 ADC R8,R1
02AA 9F38 MUL R19,R24
02AB 0C80 ADD R8,R0
02AC 9F29 MUL R18,R25
02AD 0C80 ADD R8,R0
02AE 9F1A MUL R17,R26
02AF 0C80 ADD R8,R0
02B0 9F0B MUL R16,R27
02B1 0C80 ADD R8,R0
02B2 2D0B MOV R16,R11
02B3 2D1A MOV R17,R10
02B4 2D29 MOV R18,R9
02B5 2D38 MOV R19,R8
02B6 907F POP R7
02B7 940C02EC JMP long_epilog
pop_gset2:
02B9 E0E2 LDI R30,2
02BA 940C02CB JMP pop
pop_gset4:
02BC E0E8 LDI R30,0x8
02BD 940C02CB JMP pop
push_gset5:
02BF 92FA ST R15,-Y
02C0 92EA ST R14,-Y
push_gset4:
02C1 92DA ST R13,-Y
02C2 92CA ST R12,-Y
push_gset3:
02C3 92BA ST R11,-Y
02C4 92AA ST R10,-Y
push_gset2:
02C5 937A ST R23,-Y
02C6 936A ST R22,-Y
push_gset1:
02C7 935A ST R21,-Y
02C8 934A ST R20,-Y
02C9 9508 RET
pop_gset1:
02CA E0E1 LDI R30,1
pop:
02CB 9149 LD R20,Y+
02CC 9159 LD R21,Y+
02CD FDE0 SBRC R30,0
02CE 9508 RET
02CF 9169 LD R22,Y+
02D0 9179 LD R23,Y+
02D1 FDE1 SBRC R30,1
02D2 9508 RET
02D3 90A9 LD R10,Y+
02D4 90B9 LD R11,Y+
02D5 FDE2 SBRC R30,2
02D6 9508 RET
02D7 90C9 LD R12,Y+
02D8 90D9 LD R13,Y+
02D9 FDE3 SBRC R30,3
02DA 9508 RET
02DB 90E9 LD R14,Y+
02DC 90F9 LD R15,Y+
02DD 9508 RET
long_prolog:
02DE 928A ST R8,-Y
02DF 929A ST R9,-Y
02E0 92AA ST R10,-Y
02E1 92BA ST R11,-Y
02E2 93EA ST R30,-Y
02E3 938A ST R24,-Y
02E4 939A ST R25,-Y
02E5 93AA ST R26,-Y
02E6 93BA ST R27,-Y
02E7 8589 LDD R24,Y+9
02E8 859A LDD R25,Y+10
02E9 85AB LDD R26,Y+11
02EA 85BC LDD R27,Y+12
02EB 9508 RET
long_epilog:
02EC 91B9 LD R27,Y+
02ED 91A9 LD R26,Y+
02EE 9199 LD R25,Y+
02EF 9189 LD R24,Y+
02F0 91E9 LD R30,Y+
02F1 90B9 LD R11,Y+
02F2 90A9 LD R10,Y+
02F3 9099 LD R9,Y+
02F4 9089 LD R8,Y+
02F5 9624 ADIW R28,4
02F6 9508 RET
tstzero1:
02F7 27EE CLR R30
02F8 2BE0 OR R30,R16
02F9 2BE1 OR R30,R17
02FA 2BE2 OR R30,R18
02FB 2BE3 OR R30,R19
02FC 9508 RET
tstzero2:
02FD 27EE CLR R30
02FE 2BE8 OR R30,R24
02FF 2BE9 OR R30,R25
0300 2BEA OR R30,R26
0301 2BEB OR R30,R27
0302 9508 RET
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