📄 init.s
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;;; Copyright ARM Ltd 2001. All rights reserved.
;
; This module performs ROM/RAM remapping (if required), initializes stack
; pointers and interrupts for each mode, and finally branches to __main in
; the C library (which eventually calls main()).
;
; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state,
; with IRQ and FIQ disabled.
AREA Init, CODE, READONLY
; --- Set up if ROM/RAM remapping required
; GBLL ROM_RAM_REMAP
;ROM_RAM_REMAP SETL {TRUE} ; change to {FALSE} if remapping not required
; --- ensure no functions that use semihosting SWIs are linked in from the C library
; IMPORT __use_no_semihosting_swi
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
; --- System memory locations
CM_ctl_reg EQU 0x1000000C ; Address of Core Module Control Register
Remap_bit EQU 0x04 ; Bit 2 is remap bit of CM_ctl
; --- Amount of memory (in bytes) allocated for stacks
Len_FIQ_Stack EQU 0
Len_IRQ_Stack EQU 256
Len_ABT_Stack EQU 0
Len_UND_Stack EQU 0
Len_SVC_Stack EQU 1024
Len_USR_Stack EQU 1024
; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.
Offset_FIQ_Stack EQU 0
Offset_IRQ_Stack EQU Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack EQU Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack EQU Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack EQU Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack EQU Offset_SVC_Stack + Len_SVC_Stack
ENTRY
;added by lgh
LDR r0, =0xc1000000
; MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
; SUB sp, r0, #Offset_FIQ_Stack
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
SUB sp, r0, #Offset_IRQ_Stack
; MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
; SUB sp, r0, #Offset_ABT_Stack
; MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
; SUB sp, r0, #Offset_UND_Stack
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
SUB sp, r0, #Offset_SVC_Stack
LDR r1,=0x10020000
LDR r3,=0x3FFC0000
STR r3,[r1]
LDR r1,=0x10000000
LDR r3,=0x00040304
STR r3,[r1]
LDR r1,=0x10000004
LDR r3,=0xFFFBFCFB
STR r3,[r1]
LDR r1,=0x10020004
LDR r3,=0xFFFFFFFF
STR r3,[r1]
LDR r1,=0x10027020
LDR r3,=0x31084003
STR r3,[r1]
;comment # CS0 Initialization (Async Mode)
;comment # 32-bit, ?? wait states
;setmem 0xDF001000 0x00003E00 32
;setmem 0xDF001004 0x00000E01 32
ldr r1,=0xDF001000
ldr r3,=0x00000E01
str r3,[r1]
ldr r1,=0xDF001004
ldr r3,=0x00000E01
str r3,[r1]
;comment # Setting for Memory Map IO Port
;comment # CS1 Initialization (Async Mode)
;comment # 16-bit, D0..15, ?? wait states
;setmem 0xDF001008 0x00002000 32
;setmem 0xDF00100C 0x11118501 32
ldr r1,=0xDF001008
ldr r3,=0x00002000
str r3,[r1]
ldr r1,=0xDF00100c
ldr r3,=0x11118501
str r3,[r1]
;comment # Config MUX for pin PF18->CS1
;comment # Clear PTF_GIUSE
ldr r1,=0x10015520
ldr r3,=0x00000000
str r3,[r1]
ldr r1,=0x10015538
ldr r3,=0x0000c000
str r3,[r1]
;comment # CS3 Initialization (Async Mode)
;comment # 32-bit, ?? wait states
;setmem 0xDF001018 0x00003E00 32
;setmem 0xDF00101C 0x11110601 32
; ldr r1,=0xDF001018
; ldr r3,=0x00000E00
; str r3,[r1]
; ldr r1,=0xDF00101c
; ldr r3,=0x11110601
; str r3,[r1]
;comment # FMCR Register
;comment # Select CS3 and CSD0
;setmem 0x10027814 0xFFFFFFC9 32
ldr r1,=0x10027814
ldr r3,=0xFFFFFFC9
str r3,[r1]
;comment Set Precharge Command
;setmem 0xDF000000 0x92120300 32
ldr r1,=0xDF000000
ldr r3,=0x92120300
str r3,[r1]
;comment Issue Precharge all Command
;memory 0xC0200000 +1 32
LDR r3, =0xC0200000
LDR r2, [r3]
;comment Set AutoRefresh Command
;setmem 0xDF000000 0xA2120300 32
LDR r3, =0xA2120300
STR r3, [r1]
; Issue AutoRefresh Command
LDR r3, =0xC0000000
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
;comment Set Mode Register
;setmem 0xDF000000 0xB2120300 32
LDR r3, =0xB2120300
STR r3, [r1]
;comment Issue Mode Register Command
;comment Burst Length = 8
;memory 0xC0119800 +1 32
LDR r3, =0xC0119800 ;; Mode Register Value
LDR r2, [r3]
;comment Set to Normal Mode
;comment # From the spec of the SDRAM K4S56163LC-RG75000,
;comment # 1. tRCD = 19ns minimum -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b
;comment # 2. tRP = 19ns minimum -> RP = 3 clk (SDCLK=133MHz) -> SRP = 0b
;comment # 3. tRC = 65ns minimum -> RC = 9 clk (SDCLK=133MHz) -> SRC = 1001b
;comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
;setmem 0xDF000000 0x8212F339 32
LDR r3, =0x8212F339
STR r3, [r1]
_happy
ldr r2,=0xcc800000
mov r3,#0xc000
strh r3,[r2,#0]
; ldr r2,=0x10000
;_CopyLoop1
; sub r2,r2,#1
; teq r2,#0
; beq _EndCopy
; b _CopyLoop1
;_EndCopy
; ldr r2,=0xcc800000
; mov r3,#0x0000
; strh r3,[r2,#0]
; ldr r2,=0x10000
;_CopyLoop2
; sub r2,r2,#1
; teq r2,#0
; beq _happy
; b _CopyLoop2
MSR CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit ; IRQs now enabled
SUB sp, r0, #Offset_USR_Stack
IMPORT main
; --- Now enter the C code
B main ; note use B not BL, because an application will never return this way
END
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