system.h

UCGUI在NIOS2的移植

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * C:\work\Altera\niosII_cycloneII_2c35\standard\software\hello_world_1_syslib\..\..\std_2C35.ptf
 *
 * Generated: 2006-05-25 21:08:21.914
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "std_2C35"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define ALTERA_NIOS_DEV_BOARD_CYCLONE_2C35
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_CPU_FREQ 85000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x04000020
#define NIOS2_RESET_ADDR 0x00000000

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CY7C1380_SSRAM
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_LCD_16207
#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_SYSID
#define __DDR_SDRAM_COMPONENT
#define __ALTERA_AVALON_PLL

/*
 * ext_ssram_bus configuration
 *
 */

#define EXT_SSRAM_BUS_NAME "/dev/ext_ssram_bus"
#define EXT_SSRAM_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * ext_ssram configuration
 *
 */

#define EXT_SSRAM_NAME "/dev/ext_ssram"
#define EXT_SSRAM_TYPE "altera_avalon_cy7c1380_ssram"
#define EXT_SSRAM_BASE 0x02000000
#define EXT_SSRAM_SPAN 2097152
#define EXT_SSRAM_SRAM_MEMORY_SIZE 2048
#define EXT_SSRAM_SRAM_MEMORY_UNITS 1024
#define EXT_SSRAM_SSRAM_DATA_WIDTH 32
#define EXT_SSRAM_SSRAM_READ_LATENCY 2
#define EXT_SSRAM_SIMULATION_MODEL_NUM_LANES 4
#define EXT_SSRAM_CONTENTS_INFO "SIMDIR/ext_ssram_lane1.dat 1126862409 SIMDIR/ext_ssram.dat 1126862409 SIMDIR/ext_ssram_lane3.dat 1126862409 SIMDIR/ext_ssram_lane0.dat 1126862409 SIMDIR/ext_ssram_lane2.dat 1126862409"

/*
 * ext_flash_enet_bus configuration
 *
 */

#define EXT_FLASH_ENET_BUS_NAME "/dev/ext_flash_enet_bus"
#define EXT_FLASH_ENET_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * ext_flash configuration
 *
 */

#define EXT_FLASH_NAME "/dev/ext_flash"
#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"
#define EXT_FLASH_BASE 0x00000000
#define EXT_FLASH_SPAN 16777216
#define EXT_FLASH_SETUP_VALUE 45
#define EXT_FLASH_WAIT_VALUE 160
#define EXT_FLASH_HOLD_VALUE 35
#define EXT_FLASH_TIMING_UNITS "ns"
#define EXT_FLASH_UNIT_MULTIPLIER 1
#define EXT_FLASH_SIZE 16777216
#define EXT_FLASH_CONTENTS_INFO "SIMDIR/ext_flash.dat 1126862412"

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x01000800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 5
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"
#define EPCS_CONTROLLER_CONTENTS_INFO "SIMDIR/epcs_controller_boot_rom.hex 1126862414 SIMDIR/epcs_controller_boot_rom.dat 1126862414"

/*
 * sys_clk_timer configuration
 *
 */

#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
#define SYS_CLK_TIMER_BASE 0x01001000
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_IRQ 0
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_PERIOD 10
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_FREQ 85000000

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x01001130
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 1
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0

/*
 * button_pio configuration
 *
 */

#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x01001080
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_IRQ 2
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x0000
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "ANY"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 85000000

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x01001090
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0x0000
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_FREQ 85000000

/*
 * lcd_display configuration
 *
 */

#define LCD_DISPLAY_NAME "/dev/lcd_display"
#define LCD_DISPLAY_TYPE "altera_avalon_lcd_16207"
#define LCD_DISPLAY_BASE 0x010010A0
#define LCD_DISPLAY_SPAN 16

/*
 * high_res_timer configuration
 *
 */

#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"
#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"
#define HIGH_RES_TIMER_BASE 0x01001020
#define HIGH_RES_TIMER_SPAN 32
#define HIGH_RES_TIMER_IRQ 3
#define HIGH_RES_TIMER_ALWAYS_RUN 0
#define HIGH_RES_TIMER_FIXED_PERIOD 0
#define HIGH_RES_TIMER_SNAPSHOT 1
#define HIGH_RES_TIMER_PERIOD 1
#define HIGH_RES_TIMER_PERIOD_UNITS "ms"
#define HIGH_RES_TIMER_RESET_OUTPUT 0
#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGH_RES_TIMER_MULT 0.001
#define HIGH_RES_TIMER_FREQ 85000000

/*
 * seven_seg_pio configuration
 *
 */

#define SEVEN_SEG_PIO_NAME "/dev/seven_seg_pio"
#define SEVEN_SEG_PIO_TYPE "altera_avalon_pio"
#define SEVEN_SEG_PIO_BASE 0x010010B0
#define SEVEN_SEG_PIO_SPAN 16
#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0
#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0000
#define SEVEN_SEG_PIO_HAS_TRI 0
#define SEVEN_SEG_PIO_HAS_OUT 1
#define SEVEN_SEG_PIO_HAS_IN 0
#define SEVEN_SEG_PIO_CAPTURE 0
#define SEVEN_SEG_PIO_EDGE_TYPE "NONE"
#define SEVEN_SEG_PIO_IRQ_TYPE "NONE"
#define SEVEN_SEG_PIO_FREQ 85000000

/*
 * reconfig_request_pio configuration
 *
 */

#define RECONFIG_REQUEST_PIO_NAME "/dev/reconfig_request_pio"
#define RECONFIG_REQUEST_PIO_TYPE "altera_avalon_pio"
#define RECONFIG_REQUEST_PIO_BASE 0x010010C0
#define RECONFIG_REQUEST_PIO_SPAN 16
#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0
#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0000
#define RECONFIG_REQUEST_PIO_HAS_TRI 1
#define RECONFIG_REQUEST_PIO_HAS_OUT 0
#define RECONFIG_REQUEST_PIO_HAS_IN 0
#define RECONFIG_REQUEST_PIO_CAPTURE 0
#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE"
#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE"
#define RECONFIG_REQUEST_PIO_FREQ 85000000

/*
 * uart1 configuration
 *
 */

#define UART1_NAME "/dev/uart1"
#define UART1_TYPE "altera_avalon_uart"
#define UART1_BASE 0x01001040
#define UART1_SPAN 32
#define UART1_IRQ 4
#define UART1_BAUD 115200
#define UART1_DATA_BITS 8
#define UART1_FIXED_BAUD 1
#define UART1_PARITY 'N'
#define UART1_STOP_BITS 1
#define UART1_USE_CTS_RTS 0
#define UART1_USE_EOP_REGISTER 0
#define UART1_SIM_TRUE_BAUD 0
#define UART1_SIM_CHAR_STREAM ""
#define UART1_FREQ 85000000

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x01001138
#define SYSID_SPAN 8
#define SYSID_ID 240786641u
#define SYSID_TIMESTAMP 1148434712u

/*
 * ddr_sdram configuration
 *
 */

#define DDR_SDRAM_NAME "/dev/ddr_sdram"
#define DDR_SDRAM_TYPE "ddr_sdram_component"
#define DDR_SDRAM_BASE 0x04000000
#define DDR_SDRAM_SPAN 33554432

/*
 * pll configuration
 *
 */

#define PLL_NAME "/dev/pll"
#define PLL_TYPE "altera_avalon_pll"
#define PLL_BASE 0x01001060
#define PLL_SPAN 32
#define PLL_LOCKED "None"
#define PLL_ARESET "None"
#define PLL_PLLENA "None"
#define PLL_PFDENA "None"
#define PLL_CONFIG_DONE 1

/*
 * SED1335_Data configuration
 *
 */

#define SED1335_DATA_NAME "/dev/SED1335_Data"
#define SED1335_DATA_TYPE "altera_avalon_pio"
#define SED1335_DATA_BASE 0x010010D0
#define SED1335_DATA_SPAN 16
#define SED1335_DATA_DO_TEST_BENCH_WIRING 0
#define SED1335_DATA_DRIVEN_SIM_VALUE 0x0000
#define SED1335_DATA_HAS_TRI 1
#define SED1335_DATA_HAS_OUT 0
#define SED1335_DATA_HAS_IN 0
#define SED1335_DATA_CAPTURE 0
#define SED1335_DATA_EDGE_TYPE "NONE"
#define SED1335_DATA_IRQ_TYPE "NONE"
#define SED1335_DATA_FREQ 85000000

/*
 * SED1335_WR configuration
 *
 */

#define SED1335_WR_NAME "/dev/SED1335_WR"
#define SED1335_WR_TYPE "altera_avalon_pio"
#define SED1335_WR_BASE 0x010010E0
#define SED1335_WR_SPAN 16
#define SED1335_WR_DO_TEST_BENCH_WIRING 0
#define SED1335_WR_DRIVEN_SIM_VALUE 0x0000
#define SED1335_WR_HAS_TRI 0
#define SED1335_WR_HAS_OUT 1
#define SED1335_WR_HAS_IN 0
#define SED1335_WR_CAPTURE 0
#define SED1335_WR_EDGE_TYPE "NONE"
#define SED1335_WR_IRQ_TYPE "NONE"
#define SED1335_WR_FREQ 85000000

/*
 * SED1335_RD configuration
 *
 */

#define SED1335_RD_NAME "/dev/SED1335_RD"
#define SED1335_RD_TYPE "altera_avalon_pio"
#define SED1335_RD_BASE 0x010010F0
#define SED1335_RD_SPAN 16
#define SED1335_RD_DO_TEST_BENCH_WIRING 0
#define SED1335_RD_DRIVEN_SIM_VALUE 0x0000
#define SED1335_RD_HAS_TRI 0
#define SED1335_RD_HAS_OUT 1
#define SED1335_RD_HAS_IN 0
#define SED1335_RD_CAPTURE 0
#define SED1335_RD_EDGE_TYPE "NONE"
#define SED1335_RD_IRQ_TYPE "NONE"
#define SED1335_RD_FREQ 85000000

/*
 * SED1335_CS configuration
 *
 */

#define SED1335_CS_NAME "/dev/SED1335_CS"
#define SED1335_CS_TYPE "altera_avalon_pio"
#define SED1335_CS_BASE 0x01001100
#define SED1335_CS_SPAN 16
#define SED1335_CS_DO_TEST_BENCH_WIRING 0
#define SED1335_CS_DRIVEN_SIM_VALUE 0x0000
#define SED1335_CS_HAS_TRI 0
#define SED1335_CS_HAS_OUT 1
#define SED1335_CS_HAS_IN 0
#define SED1335_CS_CAPTURE 0
#define SED1335_CS_EDGE_TYPE "NONE"
#define SED1335_CS_IRQ_TYPE "NONE"
#define SED1335_CS_FREQ 85000000

/*
 * SED1335_A configuration
 *
 */

#define SED1335_A_NAME "/dev/SED1335_A"
#define SED1335_A_TYPE "altera_avalon_pio"
#define SED1335_A_BASE 0x01001110
#define SED1335_A_SPAN 16
#define SED1335_A_DO_TEST_BENCH_WIRING 0
#define SED1335_A_DRIVEN_SIM_VALUE 0x0000
#define SED1335_A_HAS_TRI 0
#define SED1335_A_HAS_OUT 1
#define SED1335_A_HAS_IN 0
#define SED1335_A_CAPTURE 0
#define SED1335_A_EDGE_TYPE "NONE"
#define SED1335_A_IRQ_TYPE "NONE"
#define SED1335_A_FREQ 85000000

/*
 * SED1335_Rst configuration
 *
 */

#define SED1335_RST_NAME "/dev/SED1335_Rst"
#define SED1335_RST_TYPE "altera_avalon_pio"
#define SED1335_RST_BASE 0x01001120
#define SED1335_RST_SPAN 16
#define SED1335_RST_DO_TEST_BENCH_WIRING 0
#define SED1335_RST_DRIVEN_SIM_VALUE 0x0000
#define SED1335_RST_HAS_TRI 0
#define SED1335_RST_HAS_OUT 1
#define SED1335_RST_HAS_IN 0
#define SED1335_RST_CAPTURE 0
#define SED1335_RST_EDGE_TYPE "NONE"
#define SED1335_RST_IRQ_TYPE "NONE"
#define SED1335_RST_FREQ 85000000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       DDR_SDRAM
#define ALT_RODATA_DEVICE     DDR_SDRAM
#define ALT_RWDATA_DEVICE     DDR_SDRAM
#define ALT_EXCEPTIONS_DEVICE DDR_SDRAM
#define ALT_RESET_DEVICE      EXT_FLASH


#endif /* __SYSTEM_H_ */