📄 sdk7a404_startup.c
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/***********************************************************************
* $Workfile: sdk7a404_startup.c $
* $Revision: 1.2 $
* $Author: WellsK $
* $Date: Sep 09 2003 14:23:04 $
*
* Project: LogicPD SDK7A404 startup code
*
* Description:
* This file contains startup code used with the LogicPD SDK7A404
* EVB.
*
* Revision History:
* $Log: //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/bsps/sdk7a404/startup/sdk7a404_startup.c-arc $
*
* Rev 1.2 Sep 09 2003 14:23:04 WellsK
* Small tweak to code to get around optimization issues on
* GHS toolsets.
*
* Rev 1.1 Sep 05 2003 11:10:34 WellsK
* Added support for 64Mbytes SDRAM in the MMU table.
*
* Rev 1.0 Jul 01 2003 12:12:10 WellsK
* Initial revision.
*
*
***********************************************************************
* SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
* OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
* AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
* SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
*
* SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
* FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
* SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
* FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
*
* COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
* CAMAS, WA
**********************************************************************/
#include "abl_arm922t_cp15_driver.h"
#include "lh7a404_csc_driver.h"
#include "lh7a404_timer_driver.h"
#include "sdk7a404_startup.h"
#include "sdk7a404_board.h"
#include "lh7a404_smc.h"
#include "lh7a404_sdramc.h"
/***********************************************************************
* Startup code private data
**********************************************************************/
/* LogicPD SDK7A404 MMU virtual mapping table */
TT_SECTION_BLOCK_T tt_init_basic[] = {
/*******************************************************************
* 64MB of SDRAM mapped as a contiguous block.
* This is based on Micron MT48LC328M16A2 chips
******************************************************************/
/* 32 MB Bank 0 of SDRAM, contiguous, cacheable, bufferable */
{4, 0x00000000, SDRAM1_SEG1_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x00400000, SDRAM1_SEG2_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x00800000, SDRAM1_SEG3_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x00C00000, SDRAM1_SEG4_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x01000000, SDRAM1_SEG5_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x01400000, SDRAM1_SEG6_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x01800000, SDRAM1_SEG7_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x01c00000, SDRAM1_SEG8_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
/* 32 MB Bank 1 of SDRAM, contiguous, cacheable, bufferable */
{4, 0x02000000, SDRAM2_SEG1_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x02400000, SDRAM2_SEG2_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x02800000, SDRAM2_SEG3_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x02C00000, SDRAM2_SEG4_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x03000000, SDRAM2_SEG5_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x03400000, SDRAM2_SEG6_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x03800000, SDRAM2_SEG7_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
{4, 0x03c00000, SDRAM2_SEG8_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(0) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_BUFFERABLE |
ARM922T_L1D_TYPE_SECTION)},
/*******************************************************************
* 64MB of non-cached non-buffered SDRAM mapped as a contiguous
* block, based at physical address of Bank 0.
******************************************************************/
/* 32 MB Bank 0 of SDRAM, contiguous, noncacheable, nonbufferable */
{4, 0xC0000000, SDRAM1_SEG1_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC0400000, SDRAM1_SEG2_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC0800000, SDRAM1_SEG3_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC0C00000, SDRAM1_SEG4_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC1000000, SDRAM1_SEG5_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC1400000, SDRAM1_SEG6_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC1800000, SDRAM1_SEG7_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC1C00000, SDRAM1_SEG8_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
/* 32 MB Bank 1 of SDRAM, contiguous, noncacheable, nonbufferable */
{4, 0xC2000000, SDRAM2_SEG1_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC2400000, SDRAM2_SEG2_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC2800000, SDRAM2_SEG3_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC2C00000, SDRAM2_SEG4_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC3000000, SDRAM2_SEG5_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC3400000, SDRAM2_SEG6_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC3800000, SDRAM2_SEG7_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
{4, 0xC3C00000, SDRAM2_SEG8_ADDR,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(1) |
ARM922T_L1D_TYPE_SECTION)},
/* System Registers, mapped to physical address */
{1, 0x80000000, 0x80000000,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(2) |
ARM922T_L1D_TYPE_SECTION)},
/* Flash remapped to 0x90000000, cacheable */
{128, 0x90000000, SMC_CS0_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(3) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_TYPE_SECTION)},
/* Flash remapped to 0xA0000000, non-cacheable (FLASH needs to
uncached to be programmed) */
{128, 0xA0000000, SMC_CS0_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(3) |
ARM922T_L1D_CACHEABLE | ARM922T_L1D_TYPE_SECTION)},
/* Internal RAM, mapped to physical address */
{1, IRAM_BASE, IRAM_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(4) |
ARM922T_L1D_TYPE_SECTION)},
/* PCMCIA 1, mapped to physical address */
{256, SMC_CS4_BASE, SMC_CS4_BASE,
ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(5) |
ARM922T_L1D_TYPE_SECTION},
/* PCMCIA 2, mapped to physical address */
{256, SMC_CS5_BASE, SMC_CS5_BASE,
ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(5) |
ARM922T_L1D_TYPE_SECTION},
/* LAN device, mapped to physical address */
{1, LAN_BASE, LAN_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* CompactFlash memory mode interface, mapped to physical
address */
{1, CF_BASE, CF_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* EISA interface, mapped to physical address */
{1, EISA_BASE, EISA_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* Card engine register, mapped to physical address */
{1, CARDE_REG_BASE, CARDE_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* EEPROM SPI register, mapped to physical address */
{1, EE2SPI_REG_BASE, EE2SPI_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* Interrupt mask register, mapped to physical address */
{1, INTMSK_REG_BASE, INTMSK_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* Mode register, mapped to physical address */
{1, MODE_REG_BASE, MODE_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* Flash register, mapped to physical address */
{1, FLASH_REG_BASE, FLASH_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* Power management register, mapped to physical address */
{1, PWMAN_REG_BASE, PWMAN_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* CPLD revision register, mapped to physical address */
{1, CPREV_REG_BASE, CPREV_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* LED register, mapped to physical address */
{1, LED_REG_BASE, LED_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* GPIO data register, mapped to physical address */
{1, GPDAT_REG_BASE, GPDAT_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
/* GPIO data direction register, mapped to physical address */
{1, GPDIR_REG_BASE, GPDIR_REG_BASE,
(ARM922T_L1D_AP_ALL | ARM922T_L1D_DOMAIN(6) |
ARM922T_L1D_TYPE_SECTION)},
{0, 0, 0, 0} // Marks end of initialization array. Required!
};
/* When copying an image from FLASH to SDRAM for execution in SDRAM
after the MMU is enabled, this type defines the base copy address
and size of each SDRAM segment. */
typedef struct
{
UNS_32 base_address;
UNS_32 segment_size;
} SDRAM_COPY_INFO_T;
/* Number of SDRAM segments */
#define SDRAM_NUM_SEGS 8
/* Address and size of each initialized SDRAM segment before the MMU
is enabled */
const SDRAM_COPY_INFO_T sdram_copy[SDRAM_NUM_SEGS ] =
{
{SDRAM1_SEG1_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG2_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG3_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG4_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG5_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG6_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG7_ADDR, SDRAM_SEG_SIZE},
{SDRAM1_SEG8_ADDR, SDRAM_SEG_SIZE}
};
/***********************************************************************
* Startup code private functions
**********************************************************************/
/***********************************************************************
*
* Function: sdk7a404_next_address
*
* Purpose:
* Returns next available SDRAM address for a contiguous memory copy
*
* Processing:
* Based on the passed address, determine the SDRAM segment the
* address is located in. If the address is not in a valid segment,
* then return the unchanged address to the caller. Otherwise,
* increment the address to the next word location and check if it
* exceeded the segment end boundary. If it didn't, return the
* incremented address to the caller. If it did exceed the segment
* boundary and the next segment is valid, find the starting address
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