📄 sdk7a404_startup_entry.s
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; $Workfile: sdk7a404_startup_entry.s $
; $Revision: 1.1 $
; $Author: WellsK $
; $Date: Sep 04 2003 16:01:30 $
;
; Project: LogicPD SDK7A404 startup code
;
; Description:
; Basic startup code for the LogicPD SDK7A404 EVB
;
; Notes:
; This version of the file is for the ARM ADS toolset.
;
; Revision history:
; $Log: //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/bsps/sdk7a404/startup/sdk7a404_startup_entry.s-arc $
;
; Rev 1.1 Sep 04 2003 16:01:30 WellsK
; Corrected value used for TLB invalidate instruction.
;
; Rev 1.0 Jul 01 2003 12:12:10 WellsK
; Initial revision.
;
;
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; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
;
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
;
; COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
; CAMAS, WA
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export arm922t_reset
extern sdk7a404_init
; This is the user application that is called by the startup code
; once board initialization is complete
extern c_entry
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; Private defines and data
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MODE_USR EQU 0x010
MODE_FIQ EQU 0x011
MODE_IRQ EQU 0x012
MODE_SVC EQU 0x013
MODE_ABORT EQU 0x017
MODE_UNDEF EQU 0x01b
MODE_SYSTEM EQU 0x01f
MODE_BITS EQU 0x01f
I_MASK EQU 0x080
F_MASK EQU 0x040
; Initial stack until the MMU is enabled
INITIAL_STK_ADDR EQU 0xB0013FFC
; Stacks used after the MMU is enabled - this area defines the layout
; memory used by the startup code. The defines here specify how the
; stack and MMU page table are located in memory. Note that the stacks
; are also defined in the 'C' code file (sdk7a404_startup) and are
; mirrored in that file. When making changes to the stack layout, be
; sure to change that file also.
MMU_EXTRA_ADDR EQU 0x02000000
MMU_EXTA_SIZE EQU 0x1000
MMU_USR_STK_ADDR EQU MMU_EXTRA_ADDR - MMU_EXTA_SIZE
MMU_USR_STK_SIZE EQU 0x400
MMU_FIQ_STK_ADDR EQU MMU_USR_STK_ADDR - MMU_USR_STK_SIZE
MMU_FIQ_STK_SIZE EQU 0x100
MMU_IRQ_STK_ADDR EQU MMU_FIQ_STK_ADDR - MMU_FIQ_STK_SIZE
MMU_IRQ_STK_SIZE EQU 0x300
MMU_ABT_STK_ADDR EQU MMU_IRQ_STK_ADDR - MMU_IRQ_STK_SIZE
MMU_ABT_STK_SIZE EQU 0x100
MMU_UND_STK_ADDR EQU MMU_ABT_STK_ADDR - MMU_ABT_STK_SIZE
MMU_UND_STK_SIZE EQU 0x100
MMU_SYS_STK_ADDR EQU MMU_UND_STK_ADDR - MMU_UND_STK_SIZE
MMU_SYS_STK_SIZE EQU 0x800
MMU_SVC_STK_ADDR EQU MMU_SYS_STK_ADDR - MMU_SYS_STK_SIZE
MMU_SVC_STK_SIZE EQU 0x4000
MMU_TRANS_TAB_ADDR EQU 0xCD3E0000
MMU_TRANS_TAB_SIZE EQU 0x8000
; Mask used to disable the MMU and caches
MMU_DISABLE_MASK EQU 0xFFFFEFFA
; Mask used to enable the MMU and caches
MMU_ENABLE_MASK EQU 0x00001005
AREA STARTUP, CODE ; Startup code
ENTRY
arm922t_reset
B sdk7a404_reset_handler ; Reset
arm922t_undef
B arm922t_undef
arm922t_swi
B arm922t_swi
arm922t_prefetch
B arm922t_prefetch
arm922t_abort
B arm922t_abort
NOP ; Reserved
arm922t_irq
B arm922t_irq
arm922t_fiq
B arm922t_fiq
SPACE 0x20 ; Extra space
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Function: sdk7a404_reset_handler
;
; Purpose: Reset vector entry point
;
; Description:
; Place ARM core in supervisor mode and disable interrupts. Disable
; the MMU and caches. Setup a basic stack pointer and call the
; sdk7a404_init() function to set up the memory interfaces, MMU
; table, initialize code and data regions, and any other board
; specific initialization. Setup the base address for the MMU
; translation table and enable the MMU and caches. Setup stacks for
; all ARM core modes and jump to the c_entry() function.
;
; Parameters: NA
;
; Outputs; NA
;
; Returns: NA
;
; Notes: NA
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
sdk7a404_reset_handler
; Put the processor is in system mode with interrupts disabled
MOV r0, #MODE_SVC:OR:I_MASK:OR:F_MASK
MSR cpsr_cxsf, r0
; Ensure the MMU is disabled
MRC p15, 0, r1, c1, c0, 0
LDR r2,=MMU_DISABLE_MASK
AND r1, r1, r2
MCR p15, 0, r1, c1, c0, 0
; Invalidate TLBs
MOV r1,#0
MCR p15, 0, r1, c8, c7, 0
; Invalidate both caches
MCR p15, 0, r1, c7, c7, 0
; Setup up an initial stack at the end of internal memory
LDR sp, =INITIAL_STK_ADDR
; Memory and MMU initialization
BL sdk7a404_init
; Setup the Domain Access Control as all Manager
; Make all domains open, user can impose restrictions
MVN r1, #0
MCR p15, 0, r1, c3, c0, 0
; Setup Translation Table Base
LDR r0, =MMU_TRANS_TAB_ADDR
MCR p15, 0, r0, c2, c0, 0
enable_mmu
; Setup jump to run out of cached SDRAM at location inVirtMem
LDR r5, =inVirtMem
; Enable the MMU with instruction and data caches enabled
MRC p15, 0, r1, c1, c0, 0
LDR r2,=MMU_ENABLE_MASK
ORR r1, r1, r2
MCR p15, 0, r1, c1, c0, 0
; Jump to the virtual address
MOV pc, r5
; The following NOPs are to clear the pipeline after the MMU virtual
; address jump
NOP
NOP
NOP
inVirtMem
; The code is operating out of SDRAM now and is cached and buffered
; Initialize stacks for all modes
; All interrupts disabled at core for all modes
MOV r1, #I_MASK:OR:F_MASK ; No Interrupts
; Enter FIQ mode and setup the FIQ stack pointer
ORR r0, r1, #MODE_FIQ
MSR cpsr_cxsf, r0
LDR r13, =MMU_FIQ_STK_ADDR
; Enter IRQ mode and setup the IRQ stack pointer
ORR r0, r1, #MODE_IRQ
MSR cpsr_cxsf, r0
LDR r13, =MMU_IRQ_STK_ADDR
; Enter Abort mode and setup the Abort stack pointer
ORR r0, r1, #MODE_ABORT
MSR cpsr_cxsf, r0
LDR r13, =MMU_ABT_STK_ADDR
; Enter Undefined mode and setup the Undefined stack pointer
ORR r0, r1, #MODE_UNDEF
MSR cpsr_cxsf, r0
LDR r13, =MMU_UND_STK_ADDR
; Enter System mode and setup the User/System stack pointer
ORR r0, r1, #MODE_SYSTEM
MSR cpsr_cxsf, r0
LDR r13, =MMU_SYS_STK_ADDR
; Enter SVC mode and setup the SVC stack pointer.
; This is the mode for runtime initialization.
ORR r0, r1, #MODE_SVC
MSR cpsr_cxsf, r0
LDR r13, =MMU_SVC_STK_ADDR
; Get address of application to execute
LDR pc, =c_entry
END
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