crt0_iar_lolo.s79

含t h r e a d x,u c o s 的b s p

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; $Workfile:   crt0_iar_lolo.s79  $
; $Revision:   1.0  $
; $Author:   WellsK  $
; $Date:   Apr 15 2004 16:41:14  $
; 
; Project: IAR C runtime startup code (for LOLO)
;
; Description:
;     This code sets up the basic code runtime environment for and
;     application example started with the IAR toolset. This code
;     clears out the ZI segment, initialize the stacks, and branches
;     to the c_entry() function. Most initialization is performed
;     through the IAR startup code.
;
; Revision history:
; $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/bsps/sdk7a404/examples/common/crt0_iar_lolo.s79-arc  $
;
;   Rev 1.0   Apr 15 2004 16:41:14   WellsK
;Initial revision.
; 
;  
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; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
; 
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
; 
; COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
;     CAMAS, WA
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; Macros and definitions for the whole file
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SEGMENT_ALIGN    DEFINE 2      ; Align all segments to 2^2
#define CPU_MODE_NAME   "arm"

CPU_MODE    MACRO
            CODE32
            ENDM

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS   DEFINE  0x1F       ; Bit mask for mode and int bits in CPSR
USR_MODE    DEFINE  0x10       ; User mode
FIQ_MODE    DEFINE  0x11       ; Fast Interrupt Request mode
IRQ_MODE    DEFINE  0x12       ; Interrupt Request mode
SVC_MODE    DEFINE  0x13       ; Supervisor mode
ABT_MODE    DEFINE  0x17       ; Abort mode
UND_MODE    DEFINE  0x1B       ; Undefined Instruction mode
SYS_MODE    DEFINE  0x1F       ; System mode
I_MASK      DEFINE  0x80       ; IRQ mask bit
F_MASK      DEFINE  0x40       ; FIQ mask bit
IF_MASK     DEFINE  0xC0       ; IRQ/FIQ mask bits

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; ?CSTARTUP
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    MODULE    ?CSTARTUP

; RTMODEL attributes
    RTMODEL "__endian", "little"
    RTMODEL "__thumb_aware", "enabled"
    RTMODEL "__cpu_mode", "*"               ; CPU_MODE_NAME
    RTMODEL "__code_model", "*"             ; Match all code models

    PUBLIC    _start
    PUBLIC    ?cstartup
    PUBLIC    _c_entry_exit
    PUBLIC    __crt_init
    EXTERN    __segment_init
    EXTERN    __low_level_init
    EXTERN    __call_ctors
    EXTERN    c_entry
    RSEG      IRQ_STACK:DATA(2)
    RSEG      FIQ_STACK:DATA(2)
    RSEG      ABT_STACK:DATA(2)
    RSEG      UND_STACK:DATA(2)
    RSEG      SYS_STACK:DATA(2)
    RSEG      SVC_STACK:DATA:NOROOT(2)
    RSEG      ICODE:CODE:NOROOT(2)
    RSEG      DIFUNCT(2)

    CODE32
_start
?cstartup

; Save current registers
    STMFD sp!, {lr}
    STMFD sp!, {r0 - r12, lr}

; Save the existing CPU status, and the FIQ/IRQ statuses on the stack
; to be restored on exit
    MRS r5, cpsr            ; Save existing CPU status in r5

; Initialize all stacks
    mov   r1, #IF_MASK
; FIQ stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #FIQ_MODE                ; Set FIQ mode bits
    msr    cpsr_c, r0                       ; Change the mode
    MOV    r6, sp                           ; Save stack for FIQ mode
    ldr    sp, =SFE(FIQ_STACK) & 0xFFFFFFF8 ; End of FIQ_STACK

; IRQ stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #IRQ_MODE                ; Set IRQ mode bits
    msr    cpsr_c, r0                       ; Change the mode
    MOV    r7, sp                           ; Save stack for IRQ mode
    ldr    sp, =SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK

; ABT stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #ABT_MODE                ; Set ABT mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(ABT_STACK) & 0xFFFFFFF8 ; End of ABT_STACK

; UND stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #UND_MODE                ; Set UND mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(UND_STACK) & 0xFFFFFFF8 ; End of UND_STACK

; SYS stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #SYS_MODE                ; Set SYS mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(SYS_STACK) & 0xFFFFFFF8 ; End of SYS_STACK

; Save CPU status and save other statuses
; SVC stack is the same as the original LOLO stack
    MSR cpsr_cxsf, r5       ; Back to LOLO CPU mode
    STMFD sp!, {r5 - r7}    ; Save status and FIQ/IRQ stacks

; Continue to CRT_INIT for more IAR specific system startup
    b      __crt_init

; Restore original FIQ and IRQ stacks
_c_entry_exit:
    LDMFD sp!, {r5 - r7}
    MOV r3, #IF_MASK        ; No Interrupts
    ORR r4, r3, #FIQ_MODE   ; FIQ mode
    MSR cpsr_cxsf, r4       ; FIQ mode with no interrupts
    MOV sp, r6
    ORR r4, r3, #IRQ_MODE   ; IRQ mode
    MSR cpsr_cxsf, r4       ; IRQ mode with no interrupts
    MOV sp, r7
    MSR cpsr_cxsf, r5       ; LOLO mode
    LDMFD sp!, {r0 - r12, lr, pc}
    LTORG

__crt_init:

; Initialize segments.
; __segment_init and __low_level_init are assumed to use the same
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
    ldr    r4, =__low_level_init
    ldr    r5, =after__low_level_init
    ldr    r6, =__segment_init
    ldr    r7, =after__segment_init

    mov    lr, r5
    bx     r4                               ; Call __low_level_init

    CPU_MODE
after__low_level_init:
    cmp    r0, #0
    beq    after__segment_init

    mov    lr, r7
    bx     r6

    LTORG

    CPU_MODE
after__segment_init:

; Jump to main, using BX. Set _exit as the return address.
; main may be located anywhere in memory, and be of
; either ARM or Thumb mode, since BX is used.
; main is assumed to return using BX (__interwork) if it is of
; a different mode than cstartup, otherwise it will return
; in the wrong mode, causing unpredicatble behaviour.

    ldr    r4, =c_entry
    ldr    r5, =_c_entry_exit
    mov    r0, #0                           ; No parameters 
    mov    lr, r5        
    bx     r4

    LTORG
    ENDMOD

    END