crt0_iar.s79

含t h r e a d x,u c o s 的b s p

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; $Workfile:   crt0_iar.s79  $
; $Revision:   1.0  $
; $Author:   WellsK  $
; $Date:   Apr 15 2004 16:41:14  $
; 
; Project: IAR C runtime startup code
;
; Description:
;     This code sets up the basic code runtime environment for and
;     application example started with the IAR toolset. This code
;     sets up the basic stacks and uses the IAR runtime initialization
;     code to do the rest. The application entry point is through main.
;
; Revision history:
; $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/bsps/sdk7a404/examples/common/crt0_iar.s79-arc  $
;
;   Rev 1.0   Apr 15 2004 16:41:14   WellsK
;Initial revision.
; 
;  
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; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
; 
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
; 
; COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
;     CAMAS, WA
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; Macros and definitions for the whole file
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SEGMENT_ALIGN    DEFINE 2      ; Align all segments to 2^2
#define CPU_MODE_NAME   "arm"

CPU_MODE    MACRO
            CODE32
            ENDM

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS   DEFINE  0x1F       ; Bit mask for mode and int bits in CPSR
USR_MODE    DEFINE  0x10       ; User mode
FIQ_MODE    DEFINE  0x11       ; Fast Interrupt Request mode
IRQ_MODE    DEFINE  0x12       ; Interrupt Request mode
SVC_MODE    DEFINE  0x13       ; Supervisor mode
ABT_MODE    DEFINE  0x17       ; Abort mode
UND_MODE    DEFINE  0x1B       ; Undefined Instruction mode
SYS_MODE    DEFINE  0x1F       ; System mode
I_MASK      DEFINE  0x80       ; IRQ mask bit
F_MASK      DEFINE  0x40       ; FIQ mask bit
IF_MASK     DEFINE  0xC0       ; IRQ/FIQ mask bits

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; ?CSTARTUP
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    MODULE    ?CSTARTUP

    PUBLIC    _start
    RSEG      IRQ_STACK:DATA(2)
    RSEG      FIQ_STACK:DATA(2)
    RSEG      ABT_STACK:DATA(2)
    RSEG      UND_STACK:DATA(2)
    RSEG      SYS_STACK:DATA(2)
    RSEG      SVC_STACK:DATA:NOROOT(2)
    RSEG      ICODE:CODE:NOROOT(2)
    PUBLIC    ?cstartup
    EXTERN    ?main

    CODE32
_start
?cstartup

; Initialize all stacks
    mov   r1, #IF_MASK
; FIQ stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #FIQ_MODE                ; Set FIQ mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(FIQ_STACK) & 0xFFFFFFF8 ; End of FIQ_STACK

; IRQ stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #IRQ_MODE                ; Set IRQ mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK

; ABT stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #ABT_MODE                ; Set ABT mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(ABT_STACK) & 0xFFFFFFF8 ; End of ABT_STACK

; UND stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #UND_MODE                ; Set UND mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(UND_STACK) & 0xFFFFFFF8 ; End of UND_STACK

; SYS stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #SYS_MODE                ; Set SYS mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(SYS_STACK) & 0xFFFFFFF8 ; End of SYS_STACK

; SVC stack from size defined in link map file
    MRS    r0, cpsr                         ; Original PSR value
    bic    r0, r0, #MODE_BITS               ; Clear the mode bits
    orr    r0, r1, #SVC_MODE                ; Set SVC mode bits
    msr    cpsr_c, r0                       ; Change the mode
    ldr    sp, =SFE(SVC_STACK) & 0xFFFFFFF8 ; End of SVC_STACK

; Continue to ?main for more IAR specific system startup
    ldr    r0, =?main
    bx     r0        

    LTORG

    ENDMOD

    END