cpu.v

一个用max+plus II写的很小的源码。简单但对初学还行吧

module cpu(clk,reset,address,data,MERQ,IORQ,RD,WR);
input clk;
input reset;
output [7:0] address;
inout [7:0] data;
output MERQ,IORQ,RD,WR;
reg [7:0] PC,IR,RO,R1,R2,R3;
reg T;
reg state;////////
reg A,B,alu_out;

parameter FETCH=1'b0,EXECUTE=1'b1;

assign data=WR?8'bzzzzzzzz:R0;

always @(posedge clk)
	if(!reset)
		begin
			PC<=8'b00000000;
			T<=1'b0;
			state<=FETCH;
		end
	else
		begin
			case(state)
				FETCH:
					begin
						if(T==0)
							begin
								address<=PC;
								PC<=PC+1;
								{MERQ,IORQ,RD,WR}<=4'b0101;
								T<=~T;
							end
						else
							begin
								IR<=data;
								{MERQ,IORQ,RD,WR}<=4'b1111;
								state<=EXECUTE;
								T<=~T;
							end
					end
				EXECUTE:
					begin
						case(IR[7:5])
							3'b000:
								begin
									R0<={3'b000,IR[4:0]};
									state<=FETCH;
								end
							3'b001:
								begin
									if(T==0)
										begin
											address<={3'b000,IR[4:0]};
											{MERQ,IORQ,RD,WR}<=4'b0101;
											T<=~T;
										end
									else
										begin
											R0<=data;
											{MERQ,IORQ,RD,WR}<=4'b1111;
											state<=FETCH;
											T<=~T;
										end
								end
							3'b010:
								begin
									if(T==0)
										begin
											data<=R0;
											address<={3'b000,IR[4:0]};
											T<=~T;
										end
									else
										begin
											{MERQ,IORQ,RD,WR}<=4'b0110;
											state<=FETCH;
											T<=~T;
										end
								end
							3'b011:
							3'b100:
								begin
									if(T==0)
										begin
											case(IR[3:2])
												2'b00:
													A<=R0;
												2'b01:
													A<=R1;
												2'b10:
													A<=R2;
												2'b11:
													A<=R3;
											endcase
											case(IR[1:0])
												2'b00:
													B<=R0;	
												2'b01:
													B<=R1;
												2'b10:
													B<=R2;
												2'b11:
													B<=R3;
											endcase
											T<=~T;
										end
									else
										begin
											case(IR[3:2])
												2'b00:
													R0<=alu_out;
												2'b01:
													R1<=alu_out;
												2'b10:
													R2<=alu_out;
												2'b11:
													R3<=alu_out;
											endcase
											state<=FETCH;
											T<=~T;
										end
								end
							3'b101:
								if(IR[4]==1'b0 &&