rominit.s

刚开始学习44b

/* romInit.s - Samsung 44B0X ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,18jan02,m_h  CLKCON initialization (74497), _sdata for vxWorks.res*
01e,30nov01,m_h  additional label with "_" on entry point functions
01d,15oct01,jb  Removing pre-pended underscores for new compilers (Diab/Gnu
                 elf)
01c,26apr01,m_h  fix thumb mode
01b,26apr01,m_h  convert tabs to spaces for readability
01a,12apr01,m_h  created from snds100 template.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entry
point, romInit(), is the first code executed on power-up.  It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.
在系统上电时的入口程序的代码入口:romInit()

romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h).  Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.
romInit()标记了中断,设置了初始化堆栈入口指针,STACK_ADRS在configAll.h中定义过
其他的硬件和驱动初始化在sysLib.c中的sysHwInit定义

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  This
entry point allows a parameter to be passed to romStart().
热启动定义的地址ROM_WARM_ADRS

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "Samsung KS32C50100 Microcontroller User's Manual,"
.I "Samsung KS32C5000(A)/50100 Microcontroller Application Notes."

DESCRIPTION
This header file includes the minimum configuration necessary for
an ANSI compatible file.
以下的头文件被包含进来,作为最小标准配置最小化的文件,在"vxWorks.h"中包含的.
vxCpu.h       contains CPU_FAMILY definition
vxArch.h      contains architecture specific definitions
vxParams.h    contains system parameters specified by ANSI or POSIX standards
vxTypesBase.h contains type definitions for ALL types specified by ANSI or
	      POSIX not already defined in vxArch.h
*/

#define	_ASMLANGUAGE			/*因为在vxWorks.h还要包含一些头文件*/
#include "vxWorks.h"			/* vxWorks.h - VxWorks standard definitions header */
#include "sysLib.h"				/* sysLib - system-dependent library */
#include "arch/arm/arm.h"		/* arm.h - ARM CPU flags etc */
#include "arch/arm/mmuArmLib.h"	/* mmuArmLib.h - ARM MMU library header file */
#include "config.h"				/* 和configALL.h中的进行对比 */
#include "regs.h"				/* regs.h - CPU registers */

    .data
    .globl   FUNC(copyright_wind_river)
    .long    FUNC(copyright_wind_river)

/* internals */

    .globl    FUNC(romInit)    /* start of system code */
    .globl    FUNC(sdata)      /* start of data */
    .globl    _sdata

/* externals */

    .globl    FUNC(romStart)    /* system initialization routine */

_sdata:
FUNC_LABEL(sdata)
    .asciz    "start of data"
    .balign    4

    .text
    .balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
    B    cold
    B       _romUndef
    B       _romSwi
    B       _romPrefetch
    B       _romDataAbort
    B       _romReserved              /* _romReserved */
    B       .
    B       _romFIQ              /* _romFIQ     */
    B       .

cold:
	MOV	r0, #BOOT_COLD	/* fall through to warm boot entry */
warm:
	B	start

    /* copyright notice appears at beginning of ROM (in TEXT segment) */
    
    .ascii   "Copyright 1984-2001 Wind River Systems, Inc."
    .balign 4

start:
	/****************************************************
	 *disable interrupts in CPU and switch to SVC32 mode*
	 ****************************************************/	

	MRS	r1, cpsr
	BIC	r1, r1, #MASK_MODE						/*defined in arm.h - ARM CPU flags etc */
	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT		/*defined in arm.h - ARM CPU flags etc */
	MSR	cpsr, r1
	
	/* Save starttype in r13 so that r0 can be used for other purposes */
	MOV	r13, r0	

	/****************************************************
	 *关闭所有CPU中断源       							*
	 ****************************************************/
	LDR	r2, L$_S3C44B0Intmsk	/* 把中断控制寄存器的地址赋给R2 */
	MVN	r1, #0					/* 屏蔽全部中断源x07ffffff &FFFFFFFF */
	STR	r1, [r2]				/*  */

	/*
	 * If not BOOT_COLD, bypass memory configuration, memory region
	 * switching etc.
	 */
	CMP	r0, #BOOT_COLD
	BNE	HiPosn				/*不相等则跳,一般这里是相等的*/

	/*
	 * We are now executing in the normal (higher, still in ROM)
	 * position in the memory map.  Remap memory to post-reset state,
	 * so that the ROM is not now dual-mapped to zero upwards, but
	 * RAM is mapped from zero, instead.
	 */

	MOV	r0, #DRAM_TYPE		/* R0-> DRAM type */
	CMP	r0, #0x01			/* SDRAM = 0x01, EDO DRAM = 0x00 */
	BNE	EDO_RAM				/* 根据预定义判断进入SDRAM,或者是EDORAM程序分支*/
				
	
/****************************************SYNC_DRAM START****************************************/
SYNC_DRAM:

	LDR	r0, L$_S3C44B0Syscfg
	LDR	r1, L$_SysCfgSdram
	STR	r1, [r0] 			/* Cache,WB disable */

/* ROM and RAM Configuration(Multiple Load and Store).  Multiple load
 * LDMIA instruction cannot be used as there is no way to load the
 * address L$_SystemInitDataSDRAM into a register (LDR Rn,=sym is broken)
 */

	LDR	r1, L$_SystemInitDataSDRAM 
	LDR	r2, L$_SystemInitDataSDRAM + 0x04
	LDR	r3, L$_SystemInitDataSDRAM + 0x08
	LDR	r4, L$_SystemInitDataSDRAM + 0x0c
	LDR	r5, L$_SystemInitDataSDRAM + 0x10
	LDR	r6, L$_SystemInitDataSDRAM + 0x14
	LDR	r7, L$_SystemInitDataSDRAM + 0x18
	LDR	r8, L$_SystemInitDataSDRAM + 0x1c
	LDR	r9, L$_SystemInitDataSDRAM + 0x20
	LDR	r10,L$_SystemInitDataSDRAM + 0x24
	LDR	r11,L$_SystemInitDataSDRAM + 0x28
	LDR	r12,L$_SystemInitDataSDRAM + 0x2c
	LDR	r13,L$_SystemInitDataSDRAM + 0x30
	LDR	r0, L$_S3C44B0BWSCON		/*S3C44B0BWSCON Offset : 0x080000 */
	STMIA	r0, {r1-r13}


/*==============================================================
 * Copy ROM image to SYNC DRAM, Change ROM and DRAM Base pointer
 *==============================================================
 */

	MOV	r0, #RESET_ROM_START 		/* Get pointer to ROM data */
	MOV	r1, #ROM_SIZE 			/* and RAM copy */
	MOV	r2, #RESET_DRAM_START		/* Copy DRAM area base */

ROM2SDRAM_COPY_LOOP:
	LDR	r3, [r0], #4
	STR	r3, [r2], #4
	SUBS	r1, r1, #4 		/* Down Count */
	BNE ROM2SDRAM_COPY_LOOP	/*不相等则继续拷贝*/

/*====================================
 * Change Base address of ROM and DRAM
 *====================================
 */
/* Multiple load LDMIA instruction cannot be used as there is 
 * no way to load the address L$_SystemInitDataSDRAM_S into a 
 * register (LDR Rn,=sym is broken)
 */
	LDR	r1, L$_SystemInitDataSDRAM_S
	LDR	r2, L$_SystemInitDataSDRAM_S + 0x04
	LDR	r3, L$_SystemInitDataSDRAM_S + 0x08
	LDR	r4, L$_SystemInitDataSDRAM_S + 0x0c
	LDR	r5, L$_SystemInitDataSDRAM_S + 0x10
	LDR	r6, L$_SystemInitDataSDRAM_S + 0x14
	LDR	r7, L$_SystemInitDataSDRAM_S + 0x18
	LDR	r8, L$_SystemInitDataSDRAM_S + 0x1c
	LDR	r9, L$_SystemInitDataSDRAM_S + 0x20
	LDR	r10,L$_SystemInitDataSDRAM_S + 0x24
	LDR	r11,L$_SystemInitDataSDRAM_S + 0x28
	LDR	r12,L$_SystemInitDataSDRAM_S + 0x2c
	LDR	r13,L$_SystemInitDataSDRAM_S + 0x30
	LDR	r0, L$_S3C44B0BWSCON 	/*S3C44B0BWSCON Offset : 0x080000 */
	STMIA	r0, {r1-r13}
	LDR	PC, L$_HiPosn	

/****************************************SYNC_DRAM END****************************************/


/****************************************EDO_RAM START****************************************/
EDO_RAM:

	LDR	r0, L$_S3C44B0Syscfg
	LDR	r1, L$_SysCfg
	STR	r1, [r0]
/* ROM and RAM Configuration(Multiple Load and Store)
 * Multiple load LDMIA instruction cannot be used as there is 
 * no way to load the address L$_SystemInitData into a 
 * register (LDR Rn,=sym is broken)
 */

	LDR	r1, L$_SystemInitData 
	LDR	r2, L$_SystemInitData + 0x04
	LDR	r3, L$_SystemInitData + 0x08
	LDR	r4, L$_SystemInitData + 0x0c
	LDR	r5, L$_SystemInitData + 0x10
	LDR	r6, L$_SystemInitData + 0x14
	LDR	r7, L$_SystemInitData + 0x18
	LDR	r8, L$_SystemInitData + 0x1c
	LDR	r9, L$_SystemInitData + 0x20
	LDR	r10,L$_SystemInitData + 0x24
	LDR	r11,L$_SystemInitData + 0x28
	LDR	r12,L$_SystemInitData + 0x2c
	LDR	r13,L$_SystemInitData + 0x30
	LDR	r0, L$_S3C44B0BWSCON	/*S3C44B0BWSCON Offset : 0x080000 */
	STMIA	r0, {r1-r13}

/*=============================================================
 * Copy ROM image to EDO DRAM, Change ROM and DRAM Base pointer
 *=============================================================
 */
	MOV	r0, #RESET_ROM_START 		/* Get pointer to ROM data */
	MOV	r1, #ROM_SIZE			/* and RAM copy */
	MOV	r2, #RESET_DRAM_START		/* Copy DRAM area base */

ROM2DRAM_COPY_LOOP:
	LDR	r3, [r0], #4
	STR	r3, [r2], #4
	SUBS	r1, r1, #4			/* Down Count */
	BNE	ROM2DRAM_COPY_LOOP

/*====================================
 * Change Base address of ROM and DRAM
 *====================================
 */
/* Multiple load LDMIA instruction cannot be used as there is 
 * no way to load the address L$_SystemInitData_S into a 
 * register (LDR Rn,=sym is broken)
 */
	LDR	r1, L$_SystemInitData_S 
	LDR	r2, L$_SystemInitData_S + 0x04
	LDR	r3, L$_SystemInitData_S + 0x08
	LDR	r4, L$_SystemInitData_S + 0x0c
	LDR	r5, L$_SystemInitData_S + 0x10
	LDR	r6, L$_SystemInitData_S + 0x14
	LDR	r7, L$_SystemInitData_S + 0x18
	LDR	r8, L$_SystemInitData_S + 0x1c
	LDR	r9, L$_SystemInitData_S + 0x20
	LDR	r10,L$_SystemInitData_S + 0x24
	LDR	r11,L$_SystemInitData_S + 0x28
	LDR	r12,L$_SystemInitData_S + 0x2c
	LDR	r13,L$_SystemInitData_S + 0x30
 	LDR	r0, L$_S3C44B0BWSCON		/*S3C44B0BWSCON Offset : 0x080000 */
	STMIA	r0, {r1-r13}			
	LDR	PC, L$_HiPosn

/****************************************EDO_RAM END****************************************/

HiPosn:
	/*
	 * Initialize the stack pointer to just before where the
	 * uncompress code, copied from ROM to RAM, will run.
	 */

	MOV	r0, r13		/* restore starttype to r0 from r13 */
	LDR	sp, L$_STACK_ADDR
	MOV	fp, #0			/* zero frame pointer */

	/* jump to C entry point in ROM: routine - entry point + ROM base */

#if	(CPU == ARMARCH4_T)
	LDR	r12, L$_rStrtInRom
	ORR	r12, r12, #1		/* force Thumb state 强制进入Thumb状态*/
	BX	r12
#else
	LDR	pc, L$_rStrtInRom
#endif	/* (CPU == ARMARCH4_T) */

/******************************************************************************/


/*_ARM_function(romUndef)*/
_romUndef:
    SUB sp, sp, #4
    STMFD sp!, {r1}
    LDR r1, vecUndef
    STR r1, [sp, #4]
    LDMFD sp!, {r1, pc}
    
/*_ARM_function(romSwi)*/
_romSwi:
    SUB sp, sp, #4
    STMFD sp!, {r1}
    LDR r1, vecSwi
    STR r1, [sp, #4]
    LDMFD sp!, {r1, pc}

/*_ARM_function(romPrefetch)*/
_romPrefetch:
    SUB sp, sp, #4
    STMFD sp!, {r1}
    LDR r1, vecPabort
    STR r1, [sp, #4]
    LDMFD sp!, {r1, pc}

/*_ARM_function(romDataAbort)*/
_romDataAbort: 
    SUB sp, sp, #4
    STMFD sp!, {r1}
    LDR r1, vecDabort
    STR r1, [sp, #4]
    LDMFD sp!, {r1, pc}
    
/*_ARM_function(romIRQ)*/
_romIRQ:  
    SUB sp, sp, #4
    STMFD sp!, {r1}
    LDR r1, vecIrq          /* load IRQVec addr to r1 */
    STR r1, [sp, #4]        /* store content(ISR addr) to stack */
    LDMFD sp!, {r1, pc}     /* pop work regs and pc (jump to ISR) */

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */
	.balign	4

L$_HiPosn:
	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)

L$_rStrtInRom:
	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$_STACK_ADDR:
	.long	STACK_ADRS

L$_S3C44B0Intmsk:
	.long S3C44B0_INTMASK
	
L$_IopModReg:
	.long S3C44B0_IOPMOD

L$_S3C44B0Syscfg:
	.long S3C44B0_SYSCFG

vecUndef:
    .long   S3C_EXC_BASE + 4

vecSwi:
    .long   S3C_EXC_BASE + 8

vecPabort:
    .long   S3C_EXC_BASE + 12

vecDabort:
    .long   S3C_EXC_BASE + 16
 
vecIrq:
    .long   S3C_EXC_BASE + 24



L$_SystemInitData:
	.long	rBWSCON		/* BANK0[16BIT],BANK1[8BIT],BANK2-7[16BIT]*/
	.long	rBANKCON0 	/* GCS0,0x00000600 */
	.long	rBANKCON1	/* GCS1,0x00007ffc */
	.long	rBANKCON2	/* GCS2,0x00007ffc */
	.long	rBANKCON3	/* GCS3,0x00007ffc */
	.long	rBANKCON4	/* GCS4,0x00007ffc */
	.long	rBANKCON5	/* GCS5,0x00007ffc */
	.long	rBANKCON6	/* GCS6,SDRAM,0x00018000 */
	.long	rBANKCON7	/* GCS7,SDRAM,0x00018000 */
	.long	rREFRESH	/* REFRESH */
	.long	rBANKSIZE	/* 0x10 */
	.long	rMRSRB6		/* 0x20 */
	.long	rMRSRB7		/* 0x20 */

L$_SystemInitData_S:
	.long	rBWSCON		/* BANK0[16BIT],BANK1[8BIT],BANK2-7[16BIT]*/
	.long	rBANKCON0 	/* GCS0,0x00000600 */
	.long	rBANKCON1	/* GCS1,0x00007ffc */
	.long	rBANKCON2	/* GCS2,0x00007ffc */
	.long	rBANKCON3	/* GCS3,0x00007ffc */
	.long	rBANKCON4	/* GCS4,0x00007ffc */
	.long	rBANKCON5	/* GCS5,0x00007ffc */
	.long	rBANKCON6	/* GCS6,SDRAM,0x00018000 */
	.long	rBANKCON7	/* GCS7,SDRAM,0x00018000 */
	.long	rREFRESH	/* REFRESH */
	.long	rBANKSIZE	/* 0x10 */
	.long	rMRSRB6		/* 0x20 */
	.long	rMRSRB7		/* 0x20 */

/*======================================================
 * SDRAM System Initialize Data (KS32C50100 only)
 *======================================================
 */
L$_SystemInitDataSDRAM:
	.long	rBWSCON		/* BANK0[16BIT],BANK1[8BIT],BANK2-7[16BIT]*/
	.long	rBANKCON0 	/* GCS0,0x00000600 */
	.long	rBANKCON1	/* GCS1,0x00007ffc */
	.long	rBANKCON2	/* GCS2,0x00007ffc */
	.long	rBANKCON3	/* GCS3,0x00007ffc */
	.long	rBANKCON4	/* GCS4,0x00007ffc */
	.long	rBANKCON5	/* GCS5,0x00007ffc */
	.long	rBANKCON6	/* GCS6,SDRAM,0x00018000 */
	.long	rBANKCON7	/* GCS7,SDRAM,0x00018000 */
	.long	rREFRESH	/* REFRESH */
	.long	rBANKSIZE	/* 0x10 */
	.long	rMRSRB6		/* 0x20 */
	.long	rMRSRB7		/* 0x20 */

L$_SystemInitDataSDRAM_S:
	.long	rBWSCON		/* BANK0[16BIT],BANK1[8BIT],BANK2-7[16BIT]*/
	.long	rBANKCON0 	/* GCS0,0x00000600 */
	.long	rBANKCON1	/* GCS1,0x00007ffc */
	.long	rBANKCON2	/* GCS2,0x00007ffc */
	.long	rBANKCON3	/* GCS3,0x00007ffc */
	.long	rBANKCON4	/* GCS4,0x00007ffc */
	.long	rBANKCON5	/* GCS5,0x00007ffc */
	.long	rBANKCON6	/* GCS6,SDRAM,0x00018000 */
	.long	rBANKCON7	/* GCS7,SDRAM,0x00018000 */
	.long	rREFRESH	/* REFRESH */
	.long	rBANKSIZE	/* 0x10 */
	.long	rMRSRB6		/* 0x20 */
	.long	rMRSRB7		/* 0x20 */

L$_pSystemInitData:
	.long	L$_SystemInitData

L$_pSystemInitData_S:
	.long	L$_SystemInitData_S

L$_pSystemInitDataSDRAM:
	.long	L$_SystemInitDataSDRAM

L$_pSystemInitDataSDRAM_S:
	.long	L$_SystemInitDataSDRAM_S

L$_RomCopySize:
    .long    L$_RomCopySize - FUNC(romInit)