wrsbcarm7.h

刚开始学习44b

#define rBANKCON6	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
							/*GCS6,SDRAM,0x00018000*/

/*******  Bank7 Control register  ****************************************/
#define B7_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B7_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B7_Tacc		0x7		/*14clk,存取周期*/
#define B7_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B7_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B7_Tpac		0x3		/*4clk,页模式存取周期*/
#define B7_PMC		0x0		/*normal(1data)*/
/*******TYPE="DRAM"********/
/*MT=01(FP DRAM),MT=10(EDO DRAM)
*#define 	B7_MT	0x2		*EDO DRAM*
*#define 	B7_Trcd	0x0
*#define	B7_Tcas	0x0
*#define	B7_Tcp	0x0
*#define	B7_SCAN	0x2		*/
/*******TYPE="SDRAM"*******/
#define	B7_MT		0x3
#define	B7_Trcd		0x0
#define	B7_SCAN		0x0

#define rBANKCON7	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
							/*GCS7,0x00018000*/						

/************************************************************************************
*	REFEXTCON : External I/O & Memory Refresh cycle Control Register				*
*	Refresh period =(2^11-refresh_counter+1)/MCLK,根据系统时钟计算sdram的刷新数率	*
*	period=15.6us, MCLK=32Mhz,REF_Counter = 2048+1-32*15.6=1549.8					*
*	REF_Counter	EQU		1425   														*
*	period=15.6us, MCLK=66Mhz,REF_Counter = 2048+1-66*15.6=1019.4					*
************************************************************************************/
#define REF_REFEN	0x1		/*刷新允许*/
#define REF_TREFMD	0x0		/*CBR(CAS before RAS)*/
#define REF_Trp		0x0		/*2clk,sdram*/
#define REF_Trc		0x1		/*5clk*/
#define REF_Tchr	0x2		/*3clk*/
#define REF_Counter	1550	

#define rREFRESH		((REF_REFEN<<23)+(REF_TREFMD<<22)+(REF_Trp<<20)+(REF_Trc<<18)+(REF_Tchr<<16)+(REF_Counter))
							/*0x0086060e*/
/********BANKSIZE******************************************************/
#define BA_SCLKEN	0x1
#define BA_BA76MAP	0x0

#define rBANKSIZE	((BA_SCLKEN<<4)+(BA_BA76MAP))
							/* 0x10 */
/********MRSRB6********************************************************/
#define B6_WBL		0x0
#define B6_TM		0x0
#define B6_CL		0x2
#define B6_BT		0x0
#define B6_BL		0x0

#define rMRSRB6	((B6_WBL<<9)+(B6_TM<<7)+(B6_CL<<4)+(B6_BT<<3)+(B6_BL))
							/* 0x20 */
/********MRSRB7********************************************************/
#define B7_WBL		0x0
#define B7_TM		0x0
#define B7_CL		0x2
#define B7_BT		0x0
#define B7_BL		0x0

#define rMRSRB7	((B7_WBL<<9)+(B7_TM<<7)+(B7_CL<<4)+(B7_BT<<3)+(B7_BL))
							/* 0x20 */
/*************************************************************************
*  						 SMRDATA		TABLES		END 				*
*************************************************************************/
/* interrupt levels */
#define INT_LVL_EXTINT0        0    /* External Interrupt0 */
#define INT_LVL_EXTINT1        1    /* External Interrupt1 */
#define INT_LVL_EXTINT2        2    /* External Interrupt2 */
#define INT_LVL_EXTINT3        3    /* External Interrupt3 */
#define INT_LVL_EXTINT4567  4    /* External Interrupt4567 */
#define INT_LVL_TICK        	5    /* TICK Interrupt */
#define INT_LVL_ZDMA0        	6    /* Ethernet controller ZDMA 0 Interrupt */
#define INT_LVL_ZDMA1        	7    /* Ethernet controller ZDMA 1 Interrupt */
#define INT_LVL_BDMA0        	8    /* Ethernet controller BDMA 0 Interrupt */
#define INT_LVL_BDMA1        	9    /* Ethernet controller BDMA 1 Interrupt */
#define INT_LVL_WDT        	10    /* WDT Interrupt3 */
#define INT_LVL_UERR01        	11    /* UERR01 Interrupt3 */
#define INT_LVL_TIMER0        	12    /* TIMER0 Interrupt */
#define INT_LVL_TIMER1        	13    /* TIMER1 Interrupt */
#define INT_LVL_TIMER2        	14    /* TIMER2 Interrupt */
#define INT_LVL_TIMER3        	15    /* TIMER3 Interrupt */
#define INT_LVL_TIMER4        	16    /* TIMER4 Interrupt */
#define INT_LVL_TIMER5        	17    /* TIMER5 Interrupt */
#define INT_LVL_URXD0        	18    /* UART 0 Receive & Error Interrupt */
#define INT_LVL_URXD1        	19    /* UART 1 Receive & Error Interrupt */
#define INT_LVL_IIC        		20    /* IIC -Bus Interrupt */
#define INT_LVL_SIO        		21    /* SIO Interrupt */
#define INT_LVL_UTXD0          	22    /* UART 0 Transmit 0 interrupt*/
#define INT_LVL_UTXD1          	23    /* UART 1 Transmit 1 interrupt */
#define INT_LVL_RTC        		24    /* RTC Interrupt */
#define INT_LVL_ADC        		25    /* ADC Interrupt  */

/* interrupt vectors */

#define INT_VEC_EXTINT0		IVEC_TO_INUM(INT_LVL_EXTINT0)    /* External Interrupt0 */
#define INT_VEC_EXTINT1		IVEC_TO_INUM(INT_LVL_EXTINT1)    /* External Interrupt1*/
#define INT_VEC_EXTINT2		IVEC_TO_INUM(INT_LVL_EXTINT2)    /* External Interrupt2*/
#define INT_VEC_EXTINT3		IVEC_TO_INUM(INT_LVL_EXTINT3)    /* External Interrupt3*/
#define INT_VEC_EXTINT4567     IVEC_TO_INUM(INT_LVL_EXTINT4567)    /* UART 0 Transmit Interrupt */
#define INT_VEC_TICK		IVEC_TO_INUM(INT_LVL_TICK)    /* TICK Interrupt */
#define INT_VEC_ZDMA0     	IVEC_TO_INUM(INT_LVL_ZDMA0)    /* Ethernet controller ZDMA 0 Interrupt */
#define INT_VEC_ZDMA1     	IVEC_TO_INUM(INT_LVL_ZDMA1)    /* Ethernet controller ZDMA 1 Interrupt */
#define INT_VEC_BDMA0      	IVEC_TO_INUM(INT_LVL_BDMA0)    /* Ethernet controller BDMA 0 Interrupt */
#define INT_VEC_BDMA1		IVEC_TO_INUM(INT_LVL_BDMA1)    /* Ethernet controller BDMA 1 Interrupt */
#define INT_VEC_WDT		IVEC_TO_INUM(INT_LVL_WDT)    /* WDT Interrupt3 */
#define INT_VEC_UERR01		IVEC_TO_INUM(INT_LVL_UERR01)    /* UERR01 Interrupt*/
#define INT_VEC_TIMER0		IVEC_TO_INUM(INT_LVL_TIMER0)    /* TIMER0 Interrupt */
#define INT_VEC_TIMER1		IVEC_TO_INUM(INT_LVL_TIMER1)    /* TIMER1 Interrupt */
#define INT_VEC_TIMER2		IVEC_TO_INUM(INT_LVL_TIMER2)    /* TIMER2 Interrupt */
#define INT_VEC_TIMER3		IVEC_TO_INUM(INT_LVL_TIMER3)    /* TIMER3 Interrupt */
#define INT_VEC_TIMER4		IVEC_TO_INUM(INT_LVL_TIMER4)    /* TIMER4 Interrupt */
#define INT_VEC_TIMER5		IVEC_TO_INUM(INT_LVL_TIMER5)    /* TIMER5 Interrupt */
#define INT_VEC_URXD0		IVEC_TO_INUM(INT_LVL_URXD0)    /* UART 0 Receive & Error Interrupt */
#define INT_VEC_URXD1		IVEC_TO_INUM(INT_LVL_URXD1)    /* UART 1 Receive & Error Interrupt */
#define INT_VEC_IIC			IVEC_TO_INUM(INT_LVL_IIC)        /* IIC -Bus Interrupt */
#define INT_VEC_SIO			IVEC_TO_INUM(INT_LVL_SIO)    /* SIO interrupt*/
#define INT_VEC_UTXD0		IVEC_TO_INUM(INT_LVL_UTXD0)    /* UART 0 Transmit 0 interrupt*/
#define INT_VEC_UTXD1		IVEC_TO_INUM(INT_LVL_UTXD1)    /* UART 1 Transmit 0 interrupt*/
#define INT_VEC_RTC			IVEC_TO_INUM(INT_LVL_RTC)    /* RTC Interrupt */
#define INT_VEC_ADC			IVEC_TO_INUM(INT_LVL_ADC)    /* ADC Interrupt  */

/**********************************************************************************************************
 * Cache Definitions
 *
 */
#define NON_CACHE_REGION    0x4000000
#define SBCARM7_CACHE_ENABLE    0x02
#define SBCARM7_CACHE_4K        0x00
#define SBCARM7_CACHE_8K        0x10
#define SBCARM7_CACHE_MODE      0x30
#define SBCARM7_WRITE_BUFF      0x04
#define SBCARM7_TAGRAM          0x11000000

/*
 * definitions for the SBCARM7 Timer:
 * two timers clocked from same source and with the same reload overhead
 */
#define SBCARM7_TIMER_SYS_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_SYS_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)

#define SYS_TIMER_CLK               (S3C44B0_CPU_SPEED)    /* Frequency of counter/timer */
#define AUX_TIMER_CLK               (S3C44B0_CPU_SPEED)    /* Frequency of counter/timer */

#define SBCARM7_RELOAD_TICKS            3        /* three ticks to reload timer */

#define SYS_TIMER_CLEAR(x)          (SBCARM7_TIMER_T1CLEAR(x))    /* sys Clk is timer 1  */
#define SYS_TIMER_CTRL(x)           (SBCARM7_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)           (SBCARM7_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)          (SBCARM7_TIMER_T1VALUE(x))
#define SBCARM7_TIMER_VALUE_MASK        0xFFFF
#define AUX_TIMER_CLEAR(x)          (SBCARM7_TIMER_T2CLEAR(x))    /* aux Clk is timer 2  */
#define AUX_TIMER_CTRL(x)           (SBCARM7_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)           (SBCARM7_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)          (SBCARM7_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER0)
#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER1)

/******************************************************************************************
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 3 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value+3))
 * max frequency = rounddown(clock_rate/(min_counter_value+3))
 * i.e.              SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz PID board can sustain a
 * maximum clock rate of 10000 to 10500. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

#define SYS_CLK_RATE_MIN      10
#define SYS_CLK_RATE_MAX      10000
#define AUX_CLK_RATE_MIN      2
#define AUX_CLK_RATE_MAX      10000
#define SBCARM7_RESET_RAM_BASE    0x1000000  /*RAM base in reset memory map */ 

/*
 * Our MAC address definition.  User can change this value as
 * per requirement.  Note, the least significant byte of the
 * address is changed to the value of the user DIP switch setting.
 * SW4-D0 is the least significant bit of this byte.  Open=0.
 */

#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }

#ifdef __cplusplus
}
#endif

#endif    /* INCsbcarm7h */