wrsbcarm7.h

刚开始学习44b

/* sbcarm7.h - WindRiver SBC ARM7 header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01f,16jul02,m_h  C++ protection
01e,04jan02,m_h  minor cleanup
01d,03dec01,m_h  remove Diab warnings
01c,27sep01,m_h  base MAC address on user DIP setting
01b,22may01,m_h  documentation
01a,12apr01,m_h  created from snds100 template.
*/

/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/

#ifndef    INCsbcarm7h
#define    INCsbcarm7h

#ifdef __cplusplus
extern "C" {
#endif

#include "sngks32c.h"

/********************************************************************/
#define TARGET_SBCARM7


#define SBCARM7_FLASH_BASE 0x1000000


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x00000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */


#define BUS                   BUS_TYPE_NONE

#define MCLK 32000000
#define S3C44B0_CPU_SPEED         MCLK    /* CPU clocked at 32 MHz. The timer */
                    /* speed is related to this */


/* definitions for the KS32C50100 UART */

#define N_S3C44B0_UART_CHANNELS     2        /* number of S3C44B0 UART chans */
#define N_SIO_CHANNELS          N_S3C44B0_UART_CHANNELS
#define N_UART_CHANNELS       N_S3C44B0_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */


/* LED Registers (write) */
#define  S3C44B0_LEDREG             S3C44B0_PDATC

/* USER DIP switch (read) */
#define  S3C44B0_USERREG            S3C44B0_PDATC
#define READ_USERDIP()              (*((volatile char *)S3C44B0_USERREG) & 0xff)

/*************************************************************************
 *
 * DRAM Memory Bank 0 area MAP for Exception vector table 
 * and Stack, User code area. 
 *
 */

#define DRAM_BASE           0x0          /* Final start address of DRAM */
#define DRAM_LIMIT          0x200000
#define RESET_DRAM_START    0xc000000    /* Start of DRAM on power-up */
#define RESET_ROM_START     0x0          /* Start of ROM on power-up */

/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0     /* Interrupt lockout value */
#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */
#define MODE_MASK    0x1F     /* Processor Mode Mask */
#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE     0x17     /* Abort Mode(ABT) */
#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE     0x10     /* User Mode(USR) */

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      32000000     /* 32MHz, S3C44B0*/
#define fMCLK          32           /* fMCLK_MHz/MHz */

/*************************************************************************
*   SMRDATA   SYSTEM MEMORY CONTROL REGISTER EQU TABLES 				 	  *
**************************************************************************/
/* -> BWSCON : Memory Bus Width register */
#define rBWSCON  		(0x11111001)

/*******  Bank0 Control register  ****************************************/
#define B0_Tacs		0x0		/*0clk,在nGCSn有效之前地址建立时间*/
#define B0_Tocs		0x0		/*0clk,在nOE上芯片选择建立时间*/
#define B0_Tacc		0x6		/*10clk,存取周期*/
#define B0_Toch		0x0		/*0clk,在nOE上芯片选择保持时间*/
#define B0_Tcah		0x0		/*0clk,在nGCSn有效地址保持时间*/
#define B0_Tpac		0x0		/*0clk,页模式存取周期*/
#define B0_PMC		0x0		/*normal(1data)*/

#define rBANKCON0  	((B0_Tacs<<13)+(B0_Tocs<<11)+(B0_Tacc<<8)+(B0_Toch<<6)+(B0_Tcah<<4)+(B0_Tpac<<2)+(B0_PMC))	
							/*GCS0,0x00000600*/
							
/*******  Bank1 Control register  ****************************************/
#define B1_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B1_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B1_Tacc		0x7		/*14clk,存取周期*/
#define B1_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B1_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B1_Tpac		0x3		/*4clk,页模式存取周期*/
#define B1_PMC		0x0		/*normal(1data)*/

#define rBANKCON1	((B1_Tacs<<13)+(B1_Tocs<<11)+(B1_Tacc<<8)+(B1_Toch<<6)+(B1_Tcah<<4)+(B1_Tpac<<2)+(B1_PMC))
							/*GCS1,0x00007ffc*/

/*******  Bank2 Control register  ****************************************/
#define B2_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B2_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B2_Tacc		0x7		/*14clk,存取周期*/
#define B2_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B2_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B2_Tpac		0x3		/*4clk,页模式存取周期*/
#define B2_PMC		0x0		/*normal(1data)*/

#define rBANKCON2	((B2_Tacs<<13)+(B2_Tocs<<11)+(B2_Tacc<<8)+(B2_Toch<<6)+(B2_Tcah<<4)+(B2_Tpac<<2)+(B2_PMC))
							/*GCS2,0x00007ffc*/
							
/*******  Bank3 Control register  ****************************************/
#define B3_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B3_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B3_Tacc		0x7		/*14clk,存取周期*/
#define B3_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B3_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B3_Tpac		0x3		/*4clk,页模式存取周期*/
#define B3_PMC		0x0		/*normal(1data)*/

#define rBANKCON3	((B3_Tacs<<13)+(B3_Tocs<<11)+(B3_Tacc<<8)+(B3_Toch<<6)+(B3_Tcah<<4)+(B3_Tpac<<2)+(B3_PMC))
							/*GCS3,0x00007ffc*/
							
/*******  Bank4 Control register  ****************************************/
#define B4_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B4_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B4_Tacc		0x7		/*14clk,存取周期*/
#define B4_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B4_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B4_Tpac		0x3		/*4clk,页模式存取周期*/
#define B4_PMC		0x0		/*normal(1data)*/

#define rBANKCON4	((B4_Tacs<<13)+(B4_Tocs<<11)+(B4_Tacc<<8)+(B4_Toch<<6)+(B4_Tcah<<4)+(B4_Tpac<<2)+(B4_PMC))
							/*GCS4,0x00007ffc*/
							
/*******  Bank5 Control register  ****************************************/
#define B5_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B5_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B5_Tacc		0x7		/*14clk,存取周期*/
#define B5_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B5_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B5_Tpac		0x3		/*4clk,页模式存取周期*/
#define B5_PMC		0x0		/*normal(1data)*/

#define rBANKCON5	((B5_Tacs<<13)+(B5_Tocs<<11)+(B5_Tacc<<8)+(B5_Toch<<6)+(B5_Tcah<<4)+(B5_Tpac<<2)+(B5_PMC))
							/*GCS5,0x00007ffc*/

/*******  Bank6 Control register  ****************************************/
#define B6_Tacs		0x3		/*4clk,在nGCSn有效之前地址建立时间*/
#define B6_Tocs		0x3		/*4clk,在nOE上芯片选择建立时间*/
#define B6_Tacc		0x7		/*14clk,存取周期*/
#define B6_Toch		0x3		/*4clk,在nOE上芯片选择保持时间*/
#define B6_Tcah		0x3		/*4clk,在nGCSn有效地址保持时间*/
#define B6_Tpac		0x3		/*4clk,页模式存取周期*/
#define B6_PMC		0x0		/*normal(1data)*/
/*******TYPE="DRAM"********
*MT=01(FP DRAM),MT=10(EDO DRAM)
*#define 	B6_MT	0x2  EDO DRAM
*#define 	B6_Trcd	0x0
*#define	B6_Tcas	0x0
*#define	B6_Tcp	0x0
*#define	B6_SCAN	0x2*/
/*******TYPE="SDRAM"*******/
#define	B6_MT		0x3
#define	B6_Trcd		0x0
#define	B6_SCAN		0x0