📄 sngks32c.h
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/* sngks32c.h - header for Samsung ks32c with ARM7 core *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01a,12apr01,m_h created from snds100 template.*/#ifndef __INCsngks32ch#define __INCsngks32ch#ifdef __cplusplusextern "C" {#endif/************************************************************************** KS32C50100 SPECIAL REGISTERS **/#define ASIC_BASE 0x1c00000/* Interrupt Control */#define INT_CNTRL_BASE (ASIC_BASE+0x4000) /*Define base of all interrupt *//* exception base */#define S3C_EXC_BASE 0x0c000100#define excEnterUndef 0x0c000100+0x0#define excEnterSwi 0x0c000100+0x4#define excEnterPrefetchAbort 0x0c000100+0x8#define excEnterDataAbort 0x0c000100+0xc#define intEnt 0x0c000100+0x14/*SYSTEM MANAGER REGISTERS *//* System */#define S3C44B0_SYSCFG (ASIC_BASE+0x000000) /*系统寄存器地址*//* Cache */#define S3C44B0_CACHBE0 (ASIC_BASE+0x000004)#define S3C44B0_CACHBE1 (ASIC_BASE+0x000008)/* Bus control */#define S3C44B0_SBUSCON (ASIC_BASE+0x040000)/* Memory control */#define S3C44B0_BWSCON (ASIC_BASE+0x080000) /**/#define S3C44B0_BANKCON0 (ASIC_BASE+0x080004) #define S3C44B0_BANKCON1 (ASIC_BASE+0x080008) /**/#define S3C44B0_BANKCON2 (ASIC_BASE+0x08000c)#define S3C44B0_BANKCON3 (ASIC_BASE+0x080010)#define S3C44B0_BANKCON4 (ASIC_BASE+0x080014)#define S3C44B0_BANKCON5 (ASIC_BASE+0x080018)#define S3C44B0_BANKCON6 (ASIC_BASE+0x08001c)#define S3C44B0_BANKCON7 (ASIC_BASE+0x080020)#define S3C44B0_REFRESH (ASIC_BASE+0x080024)#define S3C44B0_BANKSIZE (ASIC_BASE+0x080028)#define S3C44B0_MRSRB6 (ASIC_BASE+0x08002c)#define S3C44B0_MRSRB7 (ASIC_BASE+0x080030)/* I/O PORT */#define S3C44B0_PCONA (ASIC_BASE+0x0120000)#define S3C44B0_PDATA (ASIC_BASE+0x0120004)#define S3C44B0_PCONB (ASIC_BASE+0x0120008)#define S3C44B0_PDATB (ASIC_BASE+0x012000c)#define S3C44B0_PCONC (ASIC_BASE+0x0120010)#define S3C44B0_PDATC (ASIC_BASE+0x0120014)#define S3C44B0_PUPC (ASIC_BASE+0x0120018)#define S3C44B0_PCOND (ASIC_BASE+0x012001c)#define S3C44B0_PDATD (ASIC_BASE+0x0120020)#define S3C44B0_PUPD (ASIC_BASE+0x0120024)#define S3C44B0_PCONE (ASIC_BASE+0x0120028)#define S3C44B0_PDATE (ASIC_BASE+0x012002c)#define S3C44B0_PUPE (ASIC_BASE+0x0120030)#define S3C44B0_PCONF (ASIC_BASE+0x0120034)#define S3C44B0_PDATF (ASIC_BASE+0x0120038)#define S3C44B0_PUPF (ASIC_BASE+0x012003c)#define S3C44B0_PCONG (ASIC_BASE+0x0120040)#define S3C44B0_PDATG (ASIC_BASE+0x0120044)#define S3C44B0_PUPG (ASIC_BASE+0x0120048)#define S3C44B0_SPUCR (ASIC_BASE+0x012004c)#define S3C44B0_EXTINT (ASIC_BASE+0x0120050)#define S3C44B0_EXTINTPND (ASIC_BASE+0x0120054)/* WATCHDOG */#define S3C44B0_WTCON (ASIC_BASE+0x0130000)#define S3C44B0_WTDAT (ASIC_BASE+0x0130004)#define S3C44B0_WTCNT (ASIC_BASE+0x0130008)/* Timer */#define S3C44B0_TCFG0 (ASIC_BASE+0x0150000)#define S3C44B0_TCFG1 (ASIC_BASE+0x0150004)#define S3C44B0_TCON (ASIC_BASE+0x0150008)#define S3C44B0_TCNTB0 (ASIC_BASE+0x015000c)#define S3C44B0_TCMPB0 (ASIC_BASE+0x0150010)#define S3C44B0_TCNTO0 (ASIC_BASE+0x0150014)#define S3C44B0_TCNTB1 (ASIC_BASE+0x0150018)#define S3C44B0_TCMPB1 (ASIC_BASE+0x015001c)#define S3C44B0_TCNTO1 (ASIC_BASE+0x0150020)#define S3C44B0_TCNTB2 (ASIC_BASE+0x0150024)#define S3C44B0_TCMPB2 (ASIC_BASE+0x0150028)#define S3C44B0_TCNTO2 (ASIC_BASE+0x015002c)#define S3C44B0_TCNTB3 (ASIC_BASE+0x0150030)#define S3C44B0_TCMPB3 (ASIC_BASE+0x0150034)#define S3C44B0_TCNTO3 (ASIC_BASE+0x0150038)#define S3C44B0_TCNTB4 (ASIC_BASE+0x015003c)#define S3C44B0_TCMPB4 (ASIC_BASE+0x0150040)#define S3C44B0_TCNTO4 (ASIC_BASE+0x0150044)#define S3C44B0_TCNTB5 (ASIC_BASE+0x0150048)#define S3C44B0_TCNTO5 (ASIC_BASE+0x015004c)/* RTC */#define S3C44B0_RTCCON (ASIC_BASE+0x0170040)#define S3C44B0_RTCALM (ASIC_BASE+0x0170050)#define S3C44B0_ALMSEC (ASIC_BASE+0x0170054)#define S3C44B0_ALMMIN (ASIC_BASE+0x0170058)#define S3C44B0_ALMHOUR (ASIC_BASE+0x017005c)#define S3C44B0_ALMDAY (ASIC_BASE+0x0170060)#define S3C44B0_ALMMON (ASIC_BASE+0x0170064)#define S3C44B0_ALMYEAR (ASIC_BASE+0x0170068)#define S3C44B0_RTCRST (ASIC_BASE+0x017006c)#define S3C44B0_BCDSEC (ASIC_BASE+0x0170070)#define S3C44B0_BCDMIN (ASIC_BASE+0x0170074)#define S3C44B0_BCDHOUR (ASIC_BASE+0x0170078)#define S3C44B0_BCDDAY (ASIC_BASE+0x017007c)#define S3C44B0_BCDDATE (ASIC_BASE+0x0170080)#define S3C44B0_BCDMON (ASIC_BASE+0x0170084)#define S3C44B0_BCDYEAR (ASIC_BASE+0x0170088)#define S3C44B0_TICINT (ASIC_BASE+0x017008c)/* Clock & Power management */#define S3C44B0_PLLCON (ASIC_BASE+0x0180000)#define S3C44B0_CLKCON (ASIC_BASE+0x0180004)#define S3C44B0_CLKSLOW (ASIC_BASE+0x0180008)#define S3C44B0_LOCKTIME (ASIC_BASE+0x018000c)/* INT Controller registers */#define S3C44B0_INTCON (ASIC_BASE+0x0200000)#define S3C44B0_INTPEND (ASIC_BASE+0x0200004)#define S3C44B0_INTMODE (ASIC_BASE+0x0200008)#define S3C44B0_INTMASK (ASIC_BASE+0x020000c)#define S3C44B0_I_PSLV (ASIC_BASE+0x0200010) /*slave IRQ优先级*/#define S3C44B0_I_PMST (ASIC_BASE+0x0200014) /*master IRQ优先级*/#define S3C44B0_I_CSLV (ASIC_BASE+0x0200018) /*当前slave IRQ优先级*/#define S3C44B0_I_CMST (ASIC_BASE+0x020001c) /*当前master IRQ优先级*/#define S3C44B0_I_ISPR (ASIC_BASE+0x0200020) /*IRQ中断服务挂起寄存器*/#define S3C44B0_I_ISPC (ASIC_BASE+0x0200024) /*清除中断*/#define S3C44B0_F_ISPC (ASIC_BASE+0x020003c)#define S3C44B0_INTENB S3C44B0_INTMASK#define S3C44B0_INTDIS S3C44B0_INTMASK/*#define S3C44B0_INTPENDTST (ASIC_BASE+0x0200004) 看这个寄存器的功能*//* DEFINED */#define INTCON_VECTORED 0x00 /* Vectored interrupt mode */#define INTCON_NO_VECTORED 0x04 /* Non-vectored interrupt mode */#define INTCON_IRQ 0x00 /* IRQ interrupt enable */#define INTCON_No_IRQ 0x02 /* Reserved */#define INTCON_FIQ 0x00 /* FIQ interrupt enable (FIQ中断不支持向量中断模式)*/#define INTCON_NO_FIQ 0x01 /* Reserved */#define S3C44B0_INTNUMLEVELS 26 /* 中断源数向量中断移位判断时用到*/#define S3C44B0_INTCON_VEC_IRQ (INTCON_VECTORED | INTCON_IRQ |INTCON_NO_FIQ )#define S3C44B0_INTCON_NOVEC_IRQ (INTCON_NO_VECTORED| INTCON_IRQ |INTCON_NO_FIQ)#define S3C44B0_INTPEND_VAL 0x3ffffff /* 25:0 某位为1为挂起等待状态*/#define S3C44B0_INTMODE_IRQ 0x00 /* 25:0 全部设置为IRQ模式 */#define S3C44B0_INTMASK_VAL 0x7ffffff /* 26:0 设置为1为屏蔽状态*/ #define S3C44B0_IOPDATA (ASIC_BASE+0x0200038)#define S3C44B0_IOPMOD (ASIC_BASE+0x0200040) /*这两个东西暂时删不掉*//* definitions for the KS32C50100 UART */#define SERIAL_A_BASE_ADR (ASIC_BASE+0x0100000)/* UART A base address */#define SERIAL_B_BASE_ADR (ASIC_BASE+0x0104000)/* UART B base address */#define SNGKS32C_TIMER_BASE 0x0A800000 /* Address of base of timer */#ifdef __cplusplus}#endif#endif /* __INCsngks32ch */⌨️ 快捷键说明
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