📄 stm8s_tim1.ls
字号:
3758 0450 c65258 ld a,21080
3759 0453 a48f and a,#143
3760 0455 1a01 or a,(OFST+1,sp)
3761 0457 c75258 ld 21080,a
3762 ; 1374 }
3765 045a 84 pop a
3766 045b 81 ret
3802 ; 1395 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3802 ; 1396 {
3803 switch .text
3804 045c _TIM1_ForcedOC2Config:
3806 045c 88 push a
3807 00000000 OFST: set 0
3810 ; 1398 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3812 ; 1401 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3814 045d c65259 ld a,21081
3815 0460 a48f and a,#143
3816 0462 1a01 or a,(OFST+1,sp)
3817 0464 c75259 ld 21081,a
3818 ; 1402 }
3821 0467 84 pop a
3822 0468 81 ret
3858 ; 1423 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3858 ; 1424 {
3859 switch .text
3860 0469 _TIM1_ForcedOC3Config:
3862 0469 88 push a
3863 00000000 OFST: set 0
3866 ; 1426 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3868 ; 1429 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3870 046a c6525a ld a,21082
3871 046d a48f and a,#143
3872 046f 1a01 or a,(OFST+1,sp)
3873 0471 c7525a ld 21082,a
3874 ; 1430 }
3877 0474 84 pop a
3878 0475 81 ret
3914 ; 1451 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3914 ; 1452 {
3915 switch .text
3916 0476 _TIM1_ForcedOC4Config:
3918 0476 88 push a
3919 00000000 OFST: set 0
3922 ; 1454 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3924 ; 1457 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3926 0477 c6525b ld a,21083
3927 047a a48f and a,#143
3928 047c 1a01 or a,(OFST+1,sp)
3929 047e c7525b ld 21083,a
3930 ; 1458 }
3933 0481 84 pop a
3934 0482 81 ret
3970 ; 1476 void TIM1_ARRPreloadConfig(FunctionalState NewState)
3970 ; 1477 {
3971 switch .text
3972 0483 _TIM1_ARRPreloadConfig:
3976 ; 1479 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3978 ; 1482 if (NewState != DISABLE)
3980 0483 4d tnz a
3981 0484 2705 jreq L1502
3982 ; 1484 TIM1->CR1 |= TIM1_CR1_ARPE;
3984 0486 721e5250 bset 21072,#7
3987 048a 81 ret
3988 048b L1502:
3989 ; 1488 TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE);
3991 048b 721f5250 bres 21072,#7
3992 ; 1490 }
3995 048f 81 ret
4030 ; 1508 void TIM1_SelectCOM(FunctionalState NewState)
4030 ; 1509 {
4031 switch .text
4032 0490 _TIM1_SelectCOM:
4036 ; 1511 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4038 ; 1514 if (NewState != DISABLE)
4040 0490 4d tnz a
4041 0491 2705 jreq L3702
4042 ; 1516 TIM1->CR2 |= TIM1_CR2_COMS;
4044 0493 72145251 bset 21073,#2
4047 0497 81 ret
4048 0498 L3702:
4049 ; 1520 TIM1->CR2 &= (u8)(~TIM1_CR2_COMS);
4051 0498 72155251 bres 21073,#2
4052 ; 1522 }
4055 049c 81 ret
4091 ; 1539 void TIM1_CCPreloadControl(FunctionalState NewState)
4091 ; 1540 {
4092 switch .text
4093 049d _TIM1_CCPreloadControl:
4097 ; 1542 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4099 ; 1545 if (NewState != DISABLE)
4101 049d 4d tnz a
4102 049e 2705 jreq L5112
4103 ; 1547 TIM1->CR2 |= TIM1_CR2_CCPC;
4105 04a0 72105251 bset 21073,#0
4108 04a4 81 ret
4109 04a5 L5112:
4110 ; 1551 TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC);
4112 04a5 72115251 bres 21073,#0
4113 ; 1553 }
4116 04a9 81 ret
4152 ; 1571 void TIM1_OC1PreloadConfig(FunctionalState NewState)
4152 ; 1572 {
4153 switch .text
4154 04aa _TIM1_OC1PreloadConfig:
4158 ; 1574 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4160 ; 1577 if (NewState != DISABLE)
4162 04aa 4d tnz a
4163 04ab 2705 jreq L7312
4164 ; 1579 TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
4166 04ad 72165258 bset 21080,#3
4169 04b1 81 ret
4170 04b2 L7312:
4171 ; 1583 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE);
4173 04b2 72175258 bres 21080,#3
4174 ; 1585 }
4177 04b6 81 ret
4213 ; 1603 void TIM1_OC2PreloadConfig(FunctionalState NewState)
4213 ; 1604 {
4214 switch .text
4215 04b7 _TIM1_OC2PreloadConfig:
4219 ; 1606 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4221 ; 1609 if (NewState != DISABLE)
4223 04b7 4d tnz a
4224 04b8 2705 jreq L1612
4225 ; 1611 TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
4227 04ba 72165259 bset 21081,#3
4230 04be 81 ret
4231 04bf L1612:
4232 ; 1615 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE);
4234 04bf 72175259 bres 21081,#3
4235 ; 1617 }
4238 04c3 81 ret
4274 ; 1635 void TIM1_OC3PreloadConfig(FunctionalState NewState)
4274 ; 1636 {
4275 switch .text
4276 04c4 _TIM1_OC3PreloadConfig:
4280 ; 1638 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4282 ; 1641 if (NewState != DISABLE)
4284 04c4 4d tnz a
4285 04c5 2705 jreq L3022
4286 ; 1643 TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
4288 04c7 7216525a bset 21082,#3
4291 04cb 81 ret
4292 04cc L3022:
4293 ; 1647 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE);
4295 04cc 7217525a bres 21082,#3
4296 ; 1649 }
4299 04d0 81 ret
4335 ; 1668 void TIM1_OC4PreloadConfig(FunctionalState NewState)
4335 ; 1669 {
4336 switch .text
4337 04d1 _TIM1_OC4PreloadConfig:
4341 ; 1671 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4343 ; 1674 if (NewState != DISABLE)
4345 04d1 4d tnz a
4346 04d2 2705 jreq L5222
4347 ; 1676 TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
4349 04d4 7216525b bset 21083,#3
4352 04d8 81 ret
4353 04d9 L5222:
4354 ; 1680 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE);
4356 04d9 7217525b bres 21083,#3
4357 ; 1682 }
4360 04dd 81 ret
4395 ; 1699 void TIM1_OC1FastConfig(FunctionalState NewState)
4395 ; 1700 {
4396 switch .text
4397 04de _TIM1_OC1FastConfig:
4401 ; 1702 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4403 ; 1705 if (NewState != DISABLE)
4405 04de 4d tnz a
4406 04df 2705 jreq L7422
4407 ; 1707 TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
4409 04e1 72145258 bset 21080,#2
4412 04e5 81 ret
4413 04e6 L7422:
4414 ; 1711 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE);
4416 04e6 72155258 bres 21080,#2
4417 ; 1713 }
4420 04ea 81 ret
4455 ; 1732 void TIM1_OC2FastConfig(FunctionalState NewState)
4455 ; 1733 {
4456 switch .text
4457 04eb _TIM1_OC2FastConfig:
4461 ; 1735 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4463 ; 1738 if (NewState != DISABLE)
4465 04eb 4d tnz a
4466 04ec 2705 jreq L1722
4467 ; 1740 TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
4469 04ee 72145259 bset 21081,#2
4472 04f2 81 ret
4473 04f3 L1722:
4474 ; 1744 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE);
4476 04f3 72155259 bres 21081,#2
4477 ; 1746 }
4480 04f7 81 ret
4515 ; 1764 void TIM1_OC3FastConfig(FunctionalState NewState)
4515 ; 1765 {
4516 switch .text
4517 04f8 _TIM1_OC3FastConfig:
4521 ; 1767 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4523 ; 1770 if (NewState != DISABLE)
4525 04f8 4d tnz a
4526 04f9 2705 jreq L3132
4527 ; 1772 TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
4529 04fb 7214525a bset 21082,#2
4532 04ff 81 ret
4533 0500 L3132:
4534 ; 1776 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE);
4536 0500 7215525a bres 21082,#2
4537 ; 1778 }
4540 0504 81 ret
4575 ; 1796 void TIM1_OC4FastConfig(FunctionalState NewState)
4575 ; 1797 {
4576 switch .text
4577 0505 _TIM1_OC4FastConfig:
4581 ; 1799 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4583 ; 1802 if (NewState != DISABLE)
4585 0505 4d tnz a
4586 0506 2705 jreq L5332
4587 ; 1804 TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
4589 0508 7214525b bset 21083,#2
4592 050c 81 ret
4593 050d L5332:
4594 ; 1808 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxFE);
4596 050d 7215525b bres 21083,#2
4597 ; 1810 }
4600 0511 81 ret
4705 ; 1836 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
4705 ; 1837 {
4706 switch .text
4707 0512 _TIM1_GenerateEvent:
4711 ; 1839 assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));
4713 ; 1842 TIM1->EGR = (u8)TIM1_EventSource;
4715 0512 c75257 ld 21079,a
4716 ; 1843 }
4719 0515 81 ret
4755 ; 1863 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
4755 ; 1864 {
4756 switch .text
4757 0516 _TIM1_OC1PolarityConfig:
4761 ; 1866 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
4763 ; 1869 if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
4765 0516 4d tnz a
4766 0517 2705 jreq L1242
4767 ; 1871 TIM1->CCER1 |= TIM1_CCER1_CC1P;
4769 0519 7212525c bset 21084,#1
4772 051d 81 ret
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