📄 stm8s_tim1.ls
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2697 035f 9e ld a,xh
2698 0360 a160 cp a,#96
2699 0362 260e jrne L1131
2700 ; 946 TI2_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2702 0364 7b05 ld a,(OFST+5,sp)
2703 0366 88 push a
2704 0367 ae0001 ldw x,#1
2705 036a 7b03 ld a,(OFST+3,sp)
2706 036c 95 ld xh,a
2707 036d cd07d1 call L5_TI2_Config
2710 0370 200c jra L3131
2711 0372 L1131:
2712 ; 950 TI1_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2714 0372 7b05 ld a,(OFST+5,sp)
2715 0374 88 push a
2716 0375 ae0001 ldw x,#1
2717 0378 7b03 ld a,(OFST+3,sp)
2718 037a 95 ld xh,a
2719 037b cd07a1 call L3_TI1_Config
2721 037e L3131:
2722 037e 84 pop a
2723 ; 954 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
2725 037f 7b01 ld a,(OFST+1,sp)
2726 0381 ad0a call _TIM1_SelectInputTrigger
2728 ; 957 TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
2730 0383 c65252 ld a,21074
2731 0386 aa07 or a,#7
2732 0388 c75252 ld 21074,a
2733 ; 958 }
2736 038b 85 popw x
2737 038c 81 ret
2808 ; 979 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
2808 ; 980 {
2809 switch .text
2810 038d _TIM1_SelectInputTrigger:
2812 038d 88 push a
2813 00000000 OFST: set 0
2816 ; 982 assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
2818 ; 985 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
2820 038e c65252 ld a,21074
2821 0391 a48f and a,#143
2822 0393 1a01 or a,(OFST+1,sp)
2823 0395 c75252 ld 21074,a
2824 ; 986 }
2827 0398 84 pop a
2828 0399 81 ret
2864 ; 1005 void TIM1_UpdateDisableConfig(FunctionalState NewState)
2864 ; 1006 {
2865 switch .text
2866 039a _TIM1_UpdateDisableConfig:
2870 ; 1008 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2872 ; 1011 if (NewState != DISABLE)
2874 039a 4d tnz a
2875 039b 2705 jreq L5631
2876 ; 1013 TIM1->CR1 |= TIM1_CR1_UDIS;
2878 039d 72125250 bset 21072,#1
2881 03a1 81 ret
2882 03a2 L5631:
2883 ; 1017 TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
2885 03a2 72135250 bres 21072,#1
2886 ; 1019 }
2889 03a6 81 ret
2947 ; 1038 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
2947 ; 1039 {
2948 switch .text
2949 03a7 _TIM1_UpdateRequestConfig:
2953 ; 1041 assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
2955 ; 1044 if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
2957 03a7 4d tnz a
2958 03a8 2705 jreq L7141
2959 ; 1046 TIM1->CR1 |= TIM1_CR1_URS;
2961 03aa 72145250 bset 21072,#2
2964 03ae 81 ret
2965 03af L7141:
2966 ; 1050 TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
2968 03af 72155250 bres 21072,#2
2969 ; 1052 }
2972 03b3 81 ret
3008 ; 1070 void TIM1_SelectHallSensor(FunctionalState NewState)
3008 ; 1071 {
3009 switch .text
3010 03b4 _TIM1_SelectHallSensor:
3014 ; 1073 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3016 ; 1076 if (NewState != DISABLE)
3018 03b4 4d tnz a
3019 03b5 2705 jreq L1441
3020 ; 1078 TIM1->CR2 |= TIM1_CR2_TI1S;
3022 03b7 721e5251 bset 21073,#7
3025 03bb 81 ret
3026 03bc L1441:
3027 ; 1082 TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
3029 03bc 721f5251 bres 21073,#7
3030 ; 1084 }
3033 03c0 81 ret
3090 ; 1104 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
3090 ; 1105 {
3091 switch .text
3092 03c1 _TIM1_SelectOnePulseMode:
3096 ; 1107 assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
3098 ; 1110 if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
3100 03c1 4d tnz a
3101 03c2 2705 jreq L3741
3102 ; 1112 TIM1->CR1 |= TIM1_CR1_OPM;
3104 03c4 72165250 bset 21072,#3
3107 03c8 81 ret
3108 03c9 L3741:
3109 ; 1116 TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
3111 03c9 72175250 bres 21072,#3
3112 ; 1119 }
3115 03cd 81 ret
3213 ; 1144 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
3213 ; 1145 {
3214 switch .text
3215 03ce _TIM1_SelectOutputTrigger:
3217 03ce 88 push a
3218 00000000 OFST: set 0
3221 ; 1148 assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
3223 ; 1150 TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource);
3225 03cf c65251 ld a,21073
3226 03d2 a48f and a,#143
3227 03d4 1a01 or a,(OFST+1,sp)
3228 03d6 c75251 ld 21073,a
3229 ; 1151 }
3232 03d9 84 pop a
3233 03da 81 ret
3307 ; 1172 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
3307 ; 1173 {
3308 switch .text
3309 03db _TIM1_SelectSlaveMode:
3311 03db 88 push a
3312 00000000 OFST: set 0
3315 ; 1176 assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
3317 ; 1179 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode);
3319 03dc c65252 ld a,21074
3320 03df a4f8 and a,#248
3321 03e1 1a01 or a,(OFST+1,sp)
3322 03e3 c75252 ld 21074,a
3323 ; 1181 }
3326 03e6 84 pop a
3327 03e7 81 ret
3363 ; 1198 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
3363 ; 1199 {
3364 switch .text
3365 03e8 _TIM1_SelectMasterSlaveMode:
3369 ; 1201 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3371 ; 1204 if (NewState != DISABLE)
3373 03e8 4d tnz a
3374 03e9 2705 jreq L7061
3375 ; 1206 TIM1->SMCR |= TIM1_SMCR_MSM;
3377 03eb 721e5252 bset 21074,#7
3380 03ef 81 ret
3381 03f0 L7061:
3382 ; 1210 TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
3384 03f0 721f5252 bres 21074,#7
3385 ; 1212 }
3388 03f4 81 ret
3474 ; 1243 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
3474 ; 1244 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
3474 ; 1245 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
3474 ; 1246 {
3475 switch .text
3476 03f5 _TIM1_EncoderInterfaceConfig:
3478 03f5 89 pushw x
3479 00000000 OFST: set 0
3482 ; 1250 assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
3484 ; 1251 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
3486 ; 1252 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
3488 ; 1255 if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
3490 03f6 9f ld a,xl
3491 03f7 4d tnz a
3492 03f8 2706 jreq L3561
3493 ; 1257 TIM1->CCER1 |= TIM1_CCER1_CC1P;
3495 03fa 7212525c bset 21084,#1
3497 03fe 2004 jra L5561
3498 0400 L3561:
3499 ; 1261 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
3501 0400 7213525c bres 21084,#1
3502 0404 L5561:
3503 ; 1264 if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
3505 0404 7b05 ld a,(OFST+5,sp)
3506 0406 2706 jreq L7561
3507 ; 1266 TIM1->CCER1 |= TIM1_CCER1_CC2P;
3509 0408 721a525c bset 21084,#5
3511 040c 2004 jra L1661
3512 040e L7561:
3513 ; 1270 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
3515 040e 721b525c bres 21084,#5
3516 0412 L1661:
3517 ; 1273 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);
3519 0412 c65252 ld a,21074
3520 0415 a4f0 and a,#240
3521 0417 1a01 or a,(OFST+1,sp)
3522 0419 c75252 ld 21074,a
3523 ; 1276 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3525 041c c65258 ld a,21080
3526 041f a4fc and a,#252
3527 0421 aa01 or a,#1
3528 0423 c75258 ld 21080,a
3529 ; 1277 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3531 0426 c65259 ld a,21081
3532 0429 a4fc and a,#252
3533 042b aa01 or a,#1
3534 042d c75259 ld 21081,a
3535 ; 1279 }
3538 0430 85 popw x
3539 0431 81 ret
3606 ; 1303 void TIM1_PrescalerConfig(u16 Prescaler,
3606 ; 1304 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
3606 ; 1305 {
3607 switch .text
3608 0432 _TIM1_PrescalerConfig:
3610 0432 89 pushw x
3611 00000000 OFST: set 0
3614 ; 1307 assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
3616 ; 1310 TIM1->PSCRH = (u8)(Prescaler >> 8);
3618 0433 9e ld a,xh
3619 0434 c75260 ld 21088,a
3620 ; 1311 TIM1->PSCRL = (u8)(Prescaler);
3622 0437 9f ld a,xl
3623 0438 c75261 ld 21089,a
3624 ; 1314 TIM1->EGR = TIM1_PSCReloadMode;
3626 043b 7b05 ld a,(OFST+5,sp)
3627 043d c75257 ld 21079,a
3628 ; 1316 }
3631 0440 85 popw x
3632 0441 81 ret
3668 ; 1338 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
3668 ; 1339 {
3669 switch .text
3670 0442 _TIM1_CounterModeConfig:
3672 0442 88 push a
3673 00000000 OFST: set 0
3676 ; 1341 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
3678 ; 1345 TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
3680 0443 c65250 ld a,21072
3681 0446 a48f and a,#143
3682 0448 1a01 or a,(OFST+1,sp)
3683 044a c75250 ld 21072,a
3684 ; 1346 }
3687 044d 84 pop a
3688 044e 81 ret
3746 ; 1367 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3746 ; 1368 {
3747 switch .text
3748 044f _TIM1_ForcedOC1Config:
3750 044f 88 push a
3751 00000000 OFST: set 0
3754 ; 1370 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3756 ; 1373 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
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