📄 stm8s_tim1.ls
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857 016a 7b09 ld a,(OFST+6,sp)
858 016c c75267 ld 21095,a
859 ; 290 TIM1->CCR2L = (u8)(TIM1_Pulse);
861 016f 7b0a ld a,(OFST+7,sp)
862 0171 c75268 ld 21096,a
863 ; 292 }
866 0174 5b05 addw sp,#5
867 0176 81 ret
971 ; 323 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
971 ; 324 TIM1_OutputState_TypeDef TIM1_OutputState,
971 ; 325 TIM1_OutputNState_TypeDef TIM1_OutputNState,
971 ; 326 u16 TIM1_Pulse,
971 ; 327 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
971 ; 328 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
971 ; 329 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
971 ; 330 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
971 ; 331 {
972 switch .text
973 0177 _TIM1_OC3Init:
975 0177 89 pushw x
976 0178 5203 subw sp,#3
977 00000003 OFST: set 3
980 ; 334 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
982 ; 335 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
984 ; 336 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
986 ; 337 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
988 ; 338 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
990 ; 339 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
992 ; 340 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
994 ; 343 TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
996 017a c6525d ld a,21085
997 017d a4f0 and a,#240
998 017f c7525d ld 21085,a
999 ; 345 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP ));
1001 0182 7b0c ld a,(OFST+9,sp)
1002 0184 a408 and a,#8
1003 0186 6b03 ld (OFST+0,sp),a
1004 0188 7b0b ld a,(OFST+8,sp)
1005 018a a402 and a,#2
1006 018c 6b02 ld (OFST-1,sp),a
1007 018e 7b08 ld a,(OFST+5,sp)
1008 0190 a404 and a,#4
1009 0192 6b01 ld (OFST-2,sp),a
1010 0194 9f ld a,xl
1011 0195 a401 and a,#1
1012 0197 1a01 or a,(OFST-2,sp)
1013 0199 1a02 or a,(OFST-1,sp)
1014 019b 1a03 or a,(OFST+0,sp)
1015 019d ca525d or a,21085
1016 01a0 c7525d ld 21085,a
1017 ; 350 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
1019 01a3 c6525a ld a,21082
1020 01a6 a48f and a,#143
1021 01a8 1a04 or a,(OFST+1,sp)
1022 01aa c7525a ld 21082,a
1023 ; 353 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
1025 01ad c6526f ld a,21103
1026 01b0 a4cf and a,#207
1027 01b2 c7526f ld 21103,a
1028 ; 355 TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
1030 01b5 7b0e ld a,(OFST+11,sp)
1031 01b7 a420 and a,#32
1032 01b9 6b03 ld (OFST+0,sp),a
1033 01bb 7b0d ld a,(OFST+10,sp)
1034 01bd a410 and a,#16
1035 01bf 1a03 or a,(OFST+0,sp)
1036 01c1 ca526f or a,21103
1037 01c4 c7526f ld 21103,a
1038 ; 358 TIM1->CCR3H = (u8)(TIM1_Pulse >> 8);
1040 01c7 7b09 ld a,(OFST+6,sp)
1041 01c9 c75269 ld 21097,a
1042 ; 359 TIM1->CCR3L = (u8)(TIM1_Pulse);
1044 01cc 7b0a ld a,(OFST+7,sp)
1045 01ce c7526a ld 21098,a
1046 ; 361 }
1049 01d1 5b05 addw sp,#5
1050 01d3 81 ret
1124 ; 386 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
1124 ; 387 TIM1_OutputState_TypeDef TIM1_OutputState,
1124 ; 388 u16 TIM1_Pulse,
1124 ; 389 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
1124 ; 390 TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
1124 ; 391 {
1125 switch .text
1126 01d4 _TIM1_OC4Init:
1128 01d4 89 pushw x
1129 01d5 88 push a
1130 00000001 OFST: set 1
1133 ; 394 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
1135 ; 395 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
1137 ; 396 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
1139 ; 397 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
1141 ; 402 TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
1143 01d6 c6525d ld a,21085
1144 01d9 a4cf and a,#207
1145 01db c7525d ld 21085,a
1146 ; 404 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P ));
1148 01de 7b08 ld a,(OFST+7,sp)
1149 01e0 a420 and a,#32
1150 01e2 6b01 ld (OFST+0,sp),a
1151 01e4 9f ld a,xl
1152 01e5 a410 and a,#16
1153 01e7 1a01 or a,(OFST+0,sp)
1154 01e9 ca525d or a,21085
1155 01ec c7525d ld 21085,a
1156 ; 407 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode));
1158 01ef c6525b ld a,21083
1159 01f2 a48f and a,#143
1160 01f4 1a02 or a,(OFST+1,sp)
1161 01f6 c7525b ld 21083,a
1162 ; 410 if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
1164 01f9 7b09 ld a,(OFST+8,sp)
1165 01fb 270a jreq L534
1166 ; 412 TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P);
1168 01fd c6526f ld a,21103
1169 0200 aadf or a,#223
1170 0202 c7526f ld 21103,a
1172 0205 2004 jra L734
1173 0207 L534:
1174 ; 416 TIM1->OISR &= (u8)(~TIM1_OISR_OIS4);
1176 0207 721d526f bres 21103,#6
1177 020b L734:
1178 ; 420 TIM1->CCR4H = (u8)(TIM1_Pulse >> 8);
1180 020b 7b06 ld a,(OFST+5,sp)
1181 020d c7526b ld 21099,a
1182 ; 421 TIM1->CCR4L = (u8)(TIM1_Pulse);
1184 0210 7b07 ld a,(OFST+6,sp)
1185 0212 c7526c ld 21100,a
1186 ; 423 }
1189 0215 5b03 addw sp,#3
1190 0217 81 ret
1395 ; 451 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
1395 ; 452 TIM1_LockLevel_TypeDef TIM1_LockLevel,
1395 ; 453 u8 TIM1_DeadTime,
1395 ; 454 TIM1_BreakState_TypeDef TIM1_Break,
1395 ; 455 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
1395 ; 456 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
1395 ; 457 {
1396 switch .text
1397 0218 _TIM1_BDTRConfig:
1399 0218 89 pushw x
1400 00000000 OFST: set 0
1403 ; 461 assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
1405 ; 462 assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
1407 ; 463 assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
1409 ; 464 assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
1411 ; 465 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
1413 ; 468 TIM1->DTR = (u8)(TIM1_DeadTime);
1415 0219 7b05 ld a,(OFST+5,sp)
1416 021b c7526e ld 21102,a
1417 ; 472 TIM1->BKR = (u8)((u8)TIM1_OSSIState | \
1417 ; 473 (u8)TIM1_LockLevel | \
1417 ; 474 (u8)TIM1_Break | \
1417 ; 475 (u8)TIM1_BreakPolarity | \
1417 ; 476 (u8)TIM1_AutomaticOutput);
1419 021e 9f ld a,xl
1420 021f 1a01 or a,(OFST+1,sp)
1421 0221 1a06 or a,(OFST+6,sp)
1422 0223 1a07 or a,(OFST+7,sp)
1423 0225 1a08 or a,(OFST+8,sp)
1424 0227 c7526d ld 21101,a
1425 ; 478 }
1428 022a 85 popw x
1429 022b 81 ret
1631 ; 511 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
1631 ; 512 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
1631 ; 513 TIM1_ICSelection_TypeDef TIM1_ICSelection,
1631 ; 514 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
1631 ; 515 u8 TIM1_ICFilter)
1631 ; 516 {
1632 switch .text
1633 022c _TIM1_ICInit:
1635 022c 89 pushw x
1636 00000000 OFST: set 0
1639 ; 519 assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
1641 ; 520 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
1643 ; 521 assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
1645 ; 522 assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
1647 ; 523 assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
1649 ; 525 if (TIM1_Channel == TIM1_CHANNEL_1)
1651 022d 9e ld a,xh
1652 022e 4d tnz a
1653 022f 2614 jrne L766
1654 ; 528 TI1_Config(TIM1_ICPolarity,
1654 ; 529 TIM1_ICSelection,
1654 ; 530 TIM1_ICFilter);
1656 0231 7b07 ld a,(OFST+7,sp)
1657 0233 88 push a
1658 0234 7b06 ld a,(OFST+6,sp)
1659 0236 97 ld xl,a
1660 0237 7b03 ld a,(OFST+3,sp)
1661 0239 95 ld xh,a
1662 023a cd07a1 call L3_TI1_Config
1664 023d 84 pop a
1665 ; 532 TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
1667 023e 7b06 ld a,(OFST+6,sp)
1668 0240 cd067f call _TIM1_SetIC1Prescaler
1671 0243 2044 jra L176
1672 0245 L766:
1673 ; 534 else if (TIM1_Channel == TIM1_CHANNEL_2)
1675 0245 7b01 ld a,(OFST+1,sp)
1676 0247 a101 cp a,#1
1677 0249 2614 jrne L376
1678 ; 537 TI2_Config(TIM1_ICPolarity,
1678 ; 538 TIM1_ICSelection,
1678 ; 539 TIM1_ICFilter);
1680 024b 7b07 ld a,(OFST+7,sp)
1681 024d 88 push a
1682 024e 7b06 ld a,(OFST+6,sp)
1683 0250 97 ld xl,a
1684 0251 7b03 ld a,(OFST+3,sp)
1685 0253 95 ld xh,a
1686 0254 cd07d1 call L5_TI2_Config
1688 0257 84 pop a
1689 ; 541 TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
1691 0258 7b06 ld a,(OFST+6,sp)
1692 025a cd068c call _TIM1_SetIC2Prescaler
1695 025d 202a jra L176
1696 025f L376:
1697 ; 543 else if (TIM1_Channel == TIM1_CHANNEL_3)
1699 025f a102 cp a,#2
1700 0261 2614 jrne L776
1701 ; 546 TI3_Config(TIM1_ICPolarity,
1701 ; 547 TIM1_ICSelection,
1701 ; 548 TIM1_ICFilter);
1703 0263 7b07 ld a,(OFST+7,sp)
1704 0265 88 push a
1705 0266 7b06 ld a,(OFST+6,sp)
1706 0268 97 ld xl,a
1707 0269 7b03 ld a,(OFST+3,sp)
1708 026b 95 ld xh,a
1709 026c cd0801 call L7_TI3_Config
1711 026f 84 pop a
1712 ; 550 TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
1714 0270 7b06 ld a,(OFST+6,sp)
1715 0272 cd0699 call _TIM1_SetIC3Prescaler
1718 0275 2012 jra L176
1719 0277 L776:
1720 ; 555 TI4_Config(TIM1_ICPolarity,
1720 ; 556 TIM1_ICSelection,
1720 ; 557 TIM1_ICFilter);
1722 0277 7b07 ld a,(OFST+7,sp)
1723 0279 88 push a
1724 027a 7b06 ld a,(OFST+6,sp)
1725 027c 97 ld xl,a
1726 027d 7b03 ld a,(OFST+3,sp)
1727 027f 95 ld xh,a
1728 0280 cd0831 call L11_TI4_Config
1730 0283 84 pop a
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