📄 stm8s_tim1.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
47 ; 69 void TIM1_DeInit(void)
47 ; 70 {
49 switch .text
50 0000 _TIM1_DeInit:
54 ; 71 TIM1->CR1 = TIM1_CR1_RESET_VALUE;
56 0000 725f5250 clr 21072
57 ; 72 TIM1->CR2 = TIM1_CR2_RESET_VALUE;
59 0004 725f5251 clr 21073
60 ; 73 TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
62 0008 725f5252 clr 21074
63 ; 74 TIM1->ETR = TIM1_ETR_RESET_VALUE;
65 000c 725f5253 clr 21075
66 ; 75 TIM1->IER = TIM1_IER_RESET_VALUE;
68 0010 725f5254 clr 21076
69 ; 76 TIM1->SR2 = TIM1_SR2_RESET_VALUE;
71 0014 725f5256 clr 21078
72 ; 78 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
74 0018 725f525c clr 21084
75 ; 79 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
77 001c 725f525d clr 21085
78 ; 81 TIM1->CCMR1 = 0x01;
80 0020 35015258 mov 21080,#1
81 ; 82 TIM1->CCMR2 = 0x01;
83 0024 35015259 mov 21081,#1
84 ; 83 TIM1->CCMR3 = 0x01;
86 0028 3501525a mov 21082,#1
87 ; 84 TIM1->CCMR4 = 0x01;
89 002c 3501525b mov 21083,#1
90 ; 86 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
92 0030 725f525c clr 21084
93 ; 87 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
95 0034 725f525d clr 21085
96 ; 88 TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
98 0038 725f5258 clr 21080
99 ; 89 TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
101 003c 725f5259 clr 21081
102 ; 90 TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
104 0040 725f525a clr 21082
105 ; 91 TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
107 0044 725f525b clr 21083
108 ; 92 TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
110 0048 725f525e clr 21086
111 ; 93 TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
113 004c 725f525f clr 21087
114 ; 94 TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
116 0050 725f5260 clr 21088
117 ; 95 TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
119 0054 725f5261 clr 21089
120 ; 96 TIM1->ARRH = TIM1_ARRH_RESET_VALUE;
122 0058 35ff5262 mov 21090,#255
123 ; 97 TIM1->ARRL = TIM1_ARRL_RESET_VALUE;
125 005c 35ff5263 mov 21091,#255
126 ; 98 TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
128 0060 725f5265 clr 21093
129 ; 99 TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
131 0064 725f5266 clr 21094
132 ; 100 TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
134 0068 725f5267 clr 21095
135 ; 101 TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
137 006c 725f5268 clr 21096
138 ; 102 TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
140 0070 725f5269 clr 21097
141 ; 103 TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
143 0074 725f526a clr 21098
144 ; 104 TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
146 0078 725f526b clr 21099
147 ; 105 TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
149 007c 725f526c clr 21100
150 ; 106 TIM1->OISR = TIM1_OISR_RESET_VALUE;
152 0080 725f526f clr 21103
153 ; 107 TIM1->EGR = 0x01; /* TIM1_EGR_UG */
155 0084 35015257 mov 21079,#1
156 ; 108 TIM1->DTR = TIM1_DTR_RESET_VALUE;
158 0088 725f526e clr 21102
159 ; 109 TIM1->BKR = TIM1_BKR_RESET_VALUE;
161 008c 725f526d clr 21101
162 ; 110 TIM1->RCR = TIM1_RCR_RESET_VALUE;
164 0090 725f5264 clr 21092
165 ; 111 TIM1->SR1 = TIM1_SR1_RESET_VALUE;
167 0094 725f5255 clr 21077
168 ; 112 }
171 0098 81 ret
280 ; 135 void TIM1_TimeBaseInit(u16 TIM1_Prescaler,
280 ; 136 TIM1_CounterMode_TypeDef TIM1_CounterMode,
280 ; 137 u16 TIM1_Period,
280 ; 138 u8 TIM1_RepetitionCounter)
280 ; 139 {
281 switch .text
282 0099 _TIM1_TimeBaseInit:
284 0099 89 pushw x
285 00000000 OFST: set 0
288 ; 142 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
290 ; 145 TIM1->ARRH = (u8)(TIM1_Period >> 8);
292 009a 7b06 ld a,(OFST+6,sp)
293 009c c75262 ld 21090,a
294 ; 146 TIM1->ARRL = (u8)(TIM1_Period);
296 009f 7b07 ld a,(OFST+7,sp)
297 00a1 c75263 ld 21091,a
298 ; 149 TIM1->PSCRH = (u8)(TIM1_Prescaler >> 8);
300 00a4 9e ld a,xh
301 00a5 c75260 ld 21088,a
302 ; 150 TIM1->PSCRL = (u8)(TIM1_Prescaler);
304 00a8 9f ld a,xl
305 00a9 c75261 ld 21089,a
306 ; 153 TIM1->CR1 = (u8)(((TIM1->CR1) & (u8)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (u8)(TIM1_CounterMode));
308 00ac c65250 ld a,21072
309 00af a48f and a,#143
310 00b1 1a05 or a,(OFST+5,sp)
311 00b3 c75250 ld 21072,a
312 ; 156 TIM1->RCR = TIM1_RepetitionCounter;
314 00b6 7b08 ld a,(OFST+8,sp)
315 00b8 c75264 ld 21092,a
316 ; 158 }
319 00bb 85 popw x
320 00bc 81 ret
605 ; 189 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
605 ; 190 TIM1_OutputState_TypeDef TIM1_OutputState,
605 ; 191 TIM1_OutputNState_TypeDef TIM1_OutputNState,
605 ; 192 u16 TIM1_Pulse,
605 ; 193 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
605 ; 194 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
605 ; 195 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
605 ; 196 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
605 ; 197 {
606 switch .text
607 00bd _TIM1_OC1Init:
609 00bd 89 pushw x
610 00be 5203 subw sp,#3
611 00000003 OFST: set 3
614 ; 199 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
616 ; 200 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
618 ; 201 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
620 ; 202 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
622 ; 203 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
624 ; 204 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
626 ; 205 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
628 ; 208 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
630 00c0 c6525c ld a,21084
631 00c3 a4f0 and a,#240
632 00c5 c7525c ld 21084,a
633 ; 210 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC1E ) | (TIM1_OutputNState & TIM1_CCER1_CC1NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC1P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC1NP ));
635 00c8 7b0c ld a,(OFST+9,sp)
636 00ca a408 and a,#8
637 00cc 6b03 ld (OFST+0,sp),a
638 00ce 7b0b ld a,(OFST+8,sp)
639 00d0 a402 and a,#2
640 00d2 6b02 ld (OFST-1,sp),a
641 00d4 7b08 ld a,(OFST+5,sp)
642 00d6 a404 and a,#4
643 00d8 6b01 ld (OFST-2,sp),a
644 00da 9f ld a,xl
645 00db a401 and a,#1
646 00dd 1a01 or a,(OFST-2,sp)
647 00df 1a02 or a,(OFST-1,sp)
648 00e1 1a03 or a,(OFST+0,sp)
649 00e3 ca525c or a,21084
650 00e6 c7525c ld 21084,a
651 ; 213 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
653 00e9 c65258 ld a,21080
654 00ec a48f and a,#143
655 00ee 1a04 or a,(OFST+1,sp)
656 00f0 c75258 ld 21080,a
657 ; 216 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
659 00f3 c6526f ld a,21103
660 00f6 a4fc and a,#252
661 00f8 c7526f ld 21103,a
662 ; 218 TIM1->OISR |= (u8)(( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | ( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
664 00fb 7b0e ld a,(OFST+11,sp)
665 00fd a402 and a,#2
666 00ff 6b03 ld (OFST+0,sp),a
667 0101 7b0d ld a,(OFST+10,sp)
668 0103 a401 and a,#1
669 0105 1a03 or a,(OFST+0,sp)
670 0107 ca526f or a,21103
671 010a c7526f ld 21103,a
672 ; 221 TIM1->CCR1H = (u8)(TIM1_Pulse >> 8);
674 010d 7b09 ld a,(OFST+6,sp)
675 010f c75265 ld 21093,a
676 ; 222 TIM1->CCR1L = (u8)(TIM1_Pulse);
678 0112 7b0a ld a,(OFST+7,sp)
679 0114 c75266 ld 21094,a
680 ; 223 }
683 0117 5b05 addw sp,#5
684 0119 81 ret
788 ; 254 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
788 ; 255 TIM1_OutputState_TypeDef TIM1_OutputState,
788 ; 256 TIM1_OutputNState_TypeDef TIM1_OutputNState,
788 ; 257 u16 TIM1_Pulse,
788 ; 258 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
788 ; 259 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
788 ; 260 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
788 ; 261 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
788 ; 262 {
789 switch .text
790 011a _TIM1_OC2Init:
792 011a 89 pushw x
793 011b 5203 subw sp,#3
794 00000003 OFST: set 3
797 ; 266 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
799 ; 267 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
801 ; 268 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
803 ; 269 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
805 ; 270 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
807 ; 271 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
809 ; 272 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
811 ; 275 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
813 011d c6525c ld a,21084
814 0120 a40f and a,#15
815 0122 c7525c ld 21084,a
816 ; 277 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC2E ) | (TIM1_OutputNState & TIM1_CCER1_CC2NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC2P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC2NP ));
818 0125 7b0c ld a,(OFST+9,sp)
819 0127 a480 and a,#128
820 0129 6b03 ld (OFST+0,sp),a
821 012b 7b0b ld a,(OFST+8,sp)
822 012d a420 and a,#32
823 012f 6b02 ld (OFST-1,sp),a
824 0131 7b08 ld a,(OFST+5,sp)
825 0133 a440 and a,#64
826 0135 6b01 ld (OFST-2,sp),a
827 0137 9f ld a,xl
828 0138 a410 and a,#16
829 013a 1a01 or a,(OFST-2,sp)
830 013c 1a02 or a,(OFST-1,sp)
831 013e 1a03 or a,(OFST+0,sp)
832 0140 ca525c or a,21084
833 0143 c7525c ld 21084,a
834 ; 281 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
836 0146 c65259 ld a,21081
837 0149 a48f and a,#143
838 014b 1a04 or a,(OFST+1,sp)
839 014d c75259 ld 21081,a
840 ; 284 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
842 0150 c6526f ld a,21103
843 0153 a4f3 and a,#243
844 0155 c7526f ld 21103,a
845 ; 286 TIM1->OISR |= (u8)((TIM1_OISR_OIS2 & TIM1_OCIdleState) | (TIM1_OISR_OIS2N & TIM1_OCNIdleState));
847 0158 7b0e ld a,(OFST+11,sp)
848 015a a408 and a,#8
849 015c 6b03 ld (OFST+0,sp),a
850 015e 7b0d ld a,(OFST+10,sp)
851 0160 a404 and a,#4
852 0162 1a03 or a,(OFST+0,sp)
853 0164 ca526f or a,21103
854 0167 c7526f ld 21103,a
855 ; 289 TIM1->CCR2H = (u8)(TIM1_Pulse >> 8);
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