📄 stm8s_uart1.ls
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1771 switch .text
1772 0276 _UART1_SendBreak:
1776 ; 664 UART1->CR2 |= UART1_CR2_SBK;
1778 0276 72105235 bset 21045,#0
1779 ; 665 }
1782 027a 81 ret
1816 ; 685 void UART1_SetAddress(u8 UART1_Address)
1816 ; 686 {
1817 switch .text
1818 027b _UART1_SetAddress:
1820 027b 88 push a
1821 00000000 OFST: set 0
1824 ; 688 assert_param(IS_UART1_ADDRESS_OK(UART1_Address));
1826 ; 691 UART1->CR4 &= ((u8)~UART1_CR4_ADD);
1828 027c c65237 ld a,21047
1829 027f a4f0 and a,#240
1830 0281 c75237 ld 21047,a
1831 ; 693 UART1->CR4 |= UART1_Address;
1833 0284 c65237 ld a,21047
1834 0287 1a01 or a,(OFST+1,sp)
1835 0289 c75237 ld 21047,a
1836 ; 694 }
1839 028c 84 pop a
1840 028d 81 ret
1874 ; 713 void UART1_SetGuardTime(u8 UART1_GuardTime)
1874 ; 714 {
1875 switch .text
1876 028e _UART1_SetGuardTime:
1880 ; 716 UART1->GTR = UART1_GuardTime;
1882 028e c75239 ld 21049,a
1883 ; 717 }
1886 0291 81 ret
1920 ; 751 void UART1_SetPrescaler(u8 UART1_Prescaler)
1920 ; 752 {
1921 switch .text
1922 0292 _UART1_SetPrescaler:
1926 ; 754 UART1->PSCR = UART1_Prescaler;
1928 0292 c7523a ld 21050,a
1929 ; 755 }
1932 0295 81 ret
2075 ; 775 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)
2075 ; 776 {
2076 switch .text
2077 0296 _UART1_GetFlagStatus:
2079 0296 89 pushw x
2080 0297 88 push a
2081 00000001 OFST: set 1
2084 ; 777 FlagStatus status = RESET;
2086 ; 780 assert_param(IS_UART1_FLAG_OK(UART1_FLAG));
2088 ; 784 if (UART1_FLAG == UART1_FLAG_LBDF)
2090 0298 a30210 cpw x,#528
2091 029b 2608 jrne L7501
2092 ; 786 if ((UART1->CR4 & (u8)UART1_FLAG) != (u8)0x00)
2094 029d 9f ld a,xl
2095 029e c45237 and a,21047
2096 02a1 271e jreq L5601
2097 ; 789 status = SET;
2099 02a3 2017 jp LC006
2100 ; 794 status = RESET;
2101 02a5 L7501:
2102 ; 797 else if (UART1_FLAG == UART1_FLAG_SBK)
2104 02a5 1e02 ldw x,(OFST+1,sp)
2105 02a7 a30101 cpw x,#257
2106 02aa 2609 jrne L7601
2107 ; 799 if ((UART1->CR2 & (u8)UART1_FLAG) != (u8)0x00)
2109 02ac c65235 ld a,21045
2110 02af 1503 bcp a,(OFST+2,sp)
2111 02b1 270d jreq L7701
2112 ; 802 status = SET;
2114 02b3 2007 jp LC006
2115 ; 807 status = RESET;
2116 02b5 L7601:
2117 ; 812 if ((UART1->SR & (u8)UART1_FLAG) != (u8)0x00)
2119 02b5 c65230 ld a,21040
2120 02b8 1503 bcp a,(OFST+2,sp)
2121 02ba 2704 jreq L7701
2122 ; 815 status = SET;
2124 02bc LC006:
2127 02bc a601 ld a,#1
2130 02be 2001 jra L5601
2131 02c0 L7701:
2132 ; 820 status = RESET;
2135 02c0 4f clr a
2136 02c1 L5601:
2137 ; 824 return status;
2141 02c1 5b03 addw sp,#3
2142 02c3 81 ret
2177 ; 859 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)
2177 ; 860 {
2178 switch .text
2179 02c4 _UART1_ClearFlag:
2183 ; 861 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));
2185 ; 864 if (UART1_FLAG == UART1_FLAG_RXNE)
2187 02c4 a30020 cpw x,#32
2188 02c7 2605 jrne L1211
2189 ; 866 UART1->SR = (u8)~(UART1_SR_RXNE);
2191 02c9 35df5230 mov 21040,#223
2194 02cd 81 ret
2195 02ce L1211:
2196 ; 871 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2198 02ce 72195237 bres 21047,#4
2199 ; 873 }
2202 02d2 81 ret
2284 ; 900 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)
2284 ; 901 {
2285 switch .text
2286 02d3 _UART1_GetITStatus:
2288 02d3 89 pushw x
2289 02d4 89 pushw x
2290 00000002 OFST: set 2
2293 ; 902 ITStatus pendingbitstatus = RESET;
2295 ; 903 u8 itpos = 0;
2297 ; 904 u8 itmask1 = 0;
2299 ; 905 u8 itmask2 = 0;
2301 ; 906 u8 enablestatus = 0;
2303 ; 909 assert_param(IS_UART1_GET_IT_OK(UART1_IT));
2305 ; 912 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
2307 02d5 9f ld a,xl
2308 02d6 a40f and a,#15
2309 02d8 5f clrw x
2310 02d9 97 ld xl,a
2311 02da a601 ld a,#1
2312 02dc 5d tnzw x
2313 02dd 2704 jreq L67
2314 02df L001:
2315 02df 48 sll a
2316 02e0 5a decw x
2317 02e1 26fc jrne L001
2318 02e3 L67:
2319 02e3 6b01 ld (OFST-1,sp),a
2320 ; 914 itmask1 = (u8)((u8)UART1_IT >> (u8)4);
2322 02e5 7b04 ld a,(OFST+2,sp)
2323 02e7 4e swap a
2324 02e8 a40f and a,#15
2325 02ea 6b02 ld (OFST+0,sp),a
2326 ; 916 itmask2 = (u8)((u8)1 << itmask1);
2328 02ec 5f clrw x
2329 02ed 97 ld xl,a
2330 02ee a601 ld a,#1
2331 02f0 5d tnzw x
2332 02f1 2704 jreq L201
2333 02f3 L401:
2334 02f3 48 sll a
2335 02f4 5a decw x
2336 02f5 26fc jrne L401
2337 02f7 L201:
2338 02f7 6b02 ld (OFST+0,sp),a
2339 ; 920 if (UART1_IT == UART1_IT_PE)
2341 02f9 1e03 ldw x,(OFST+1,sp)
2342 02fb a30100 cpw x,#256
2343 02fe 260c jrne L7611
2344 ; 923 enablestatus = (u8)((u8)UART1->CR1 & itmask2);
2346 0300 c65234 ld a,21044
2347 0303 1402 and a,(OFST+0,sp)
2348 0305 6b02 ld (OFST+0,sp),a
2349 ; 926 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2351 0307 c65230 ld a,21040
2353 ; 929 pendingbitstatus = SET;
2355 030a 200f jp LC009
2356 ; 934 pendingbitstatus = RESET;
2357 030c L7611:
2358 ; 938 else if (UART1_IT == UART1_IT_LBDF)
2360 030c a30346 cpw x,#838
2361 030f 2616 jrne L7711
2362 ; 941 enablestatus = (u8)((u8)UART1->CR4 & itmask2);
2364 0311 c65237 ld a,21047
2365 0314 1402 and a,(OFST+0,sp)
2366 0316 6b02 ld (OFST+0,sp),a
2367 ; 943 if (((UART1->CR4 & itpos) != (u8)0x00) && enablestatus)
2369 0318 c65237 ld a,21047
2371 031b LC009:
2372 031b 1501 bcp a,(OFST-1,sp)
2373 031d 271a jreq L7021
2374 031f 7b02 ld a,(OFST+0,sp)
2375 0321 2716 jreq L7021
2376 ; 946 pendingbitstatus = SET;
2378 0323 LC008:
2381 0323 a601 ld a,#1
2383 0325 2013 jra L5711
2384 ; 951 pendingbitstatus = RESET;
2385 0327 L7711:
2386 ; 957 enablestatus = (u8)((u8)UART1->CR2 & itmask2);
2388 0327 c65235 ld a,21045
2389 032a 1402 and a,(OFST+0,sp)
2390 032c 6b02 ld (OFST+0,sp),a
2391 ; 959 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2393 032e c65230 ld a,21040
2394 0331 1501 bcp a,(OFST-1,sp)
2395 0333 2704 jreq L7021
2397 0335 7b02 ld a,(OFST+0,sp)
2398 ; 962 pendingbitstatus = SET;
2400 0337 26ea jrne LC008
2401 0339 L7021:
2402 ; 967 pendingbitstatus = RESET;
2406 0339 4f clr a
2407 033a L5711:
2408 ; 972 return pendingbitstatus;
2412 033a 5b04 addw sp,#4
2413 033c 81 ret
2449 ; 1006 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)
2449 ; 1007 {
2450 switch .text
2451 033d _UART1_ClearITPendingBit:
2455 ; 1008 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_IT));
2457 ; 1011 if (UART1_IT == UART1_IT_RXNE)
2459 033d a30255 cpw x,#597
2460 0340 2605 jrne L1321
2461 ; 1013 UART1->SR = (u8)~(UART1_SR_RXNE);
2463 0342 35df5230 mov 21040,#223
2466 0346 81 ret
2467 0347 L1321:
2468 ; 1018 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2470 0347 72195237 bres 21047,#4
2471 ; 1020 }
2474 034b 81 ret
2487 xref _CLK_GetClockFreq
2488 xdef _UART1_ClearITPendingBit
2489 xdef _UART1_GetITStatus
2490 xdef _UART1_ClearFlag
2491 xdef _UART1_GetFlagStatus
2492 xdef _UART1_SetPrescaler
2493 xdef _UART1_SetGuardTime
2494 xdef _UART1_SetAddress
2495 xdef _UART1_SendBreak
2496 xdef _UART1_SendData9
2497 xdef _UART1_SendData8
2498 xdef _UART1_ReceiveData9
2499 xdef _UART1_ReceiveData8
2500 xdef _UART1_ReceiverWakeUpCmd
2501 xdef _UART1_WakeUpConfig
2502 xdef _UART1_SmartCardNACKCmd
2503 xdef _UART1_SmartCardCmd
2504 xdef _UART1_LINCmd
2505 xdef _UART1_LINBreakDetectionConfig
2506 xdef _UART1_IrDACmd
2507 xdef _UART1_IrDAConfig
2508 xdef _UART1_HalfDuplexCmd
2509 xdef _UART1_ITConfig
2510 xdef _UART1_Cmd
2511 xdef _UART1_Init
2512 xdef _UART1_DeInit
2513 xref.b c_lreg
2514 xref.b c_x
2533 xref c_lursh
2534 xref c_lsub
2535 xref c_smul
2536 xref c_ludv
2537 xref c_rtol
2538 xref c_llsh
2539 xref c_ltor
2540 end
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