📄 stm8s_uart1.ls
字号:
885 0181 2607 jrne L723
886 ; 247 UART1->CR1 |= itpos;
888 0183 c65234 ld a,21044
889 0186 1a02 or a,(OFST+0,sp)
891 0188 201e jp LC002
892 018a L723:
893 ; 249 else if (uartreg == 0x02)
895 018a a102 cp a,#2
896 018c 2607 jrne L333
897 ; 251 UART1->CR2 |= itpos;
899 018e c65235 ld a,21045
900 0191 1a02 or a,(OFST+0,sp)
902 0193 2022 jp LC003
903 0195 L333:
904 ; 255 UART1->CR4 |= itpos;
906 0195 c65237 ld a,21047
907 0198 1a02 or a,(OFST+0,sp)
908 019a 2026 jp LC001
909 019c L523:
910 ; 261 if (uartreg == 0x01)
912 019c 7b01 ld a,(OFST-1,sp)
913 019e a101 cp a,#1
914 01a0 260b jrne L143
915 ; 263 UART1->CR1 &= (u8)(~itpos);
917 01a2 7b02 ld a,(OFST+0,sp)
918 01a4 43 cpl a
919 01a5 c45234 and a,21044
920 01a8 LC002:
921 01a8 c75234 ld 21044,a
923 01ab 2018 jra L733
924 01ad L143:
925 ; 265 else if (uartreg == 0x02)
927 01ad a102 cp a,#2
928 01af 260b jrne L543
929 ; 267 UART1->CR2 &= (u8)(~itpos);
931 01b1 7b02 ld a,(OFST+0,sp)
932 01b3 43 cpl a
933 01b4 c45235 and a,21045
934 01b7 LC003:
935 01b7 c75235 ld 21045,a
937 01ba 2009 jra L733
938 01bc L543:
939 ; 271 UART1->CR4 &= (u8)(~itpos);
941 01bc 7b02 ld a,(OFST+0,sp)
942 01be 43 cpl a
943 01bf c45237 and a,21047
944 01c2 LC001:
945 01c2 c75237 ld 21047,a
946 01c5 L733:
947 ; 275 }
950 01c5 5b04 addw sp,#4
951 01c7 81 ret
987 ; 292 void UART1_HalfDuplexCmd(FunctionalState NewState)
987 ; 293 {
988 switch .text
989 01c8 _UART1_HalfDuplexCmd:
993 ; 294 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
995 ; 296 if (NewState != DISABLE)
997 01c8 4d tnz a
998 01c9 2705 jreq L763
999 ; 298 UART1->CR5 |= UART1_CR5_HDSEL; /**< UART1 Half Duplex Enable */
1001 01cb 72165238 bset 21048,#3
1004 01cf 81 ret
1005 01d0 L763:
1006 ; 302 UART1->CR5 &= (u8)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */
1008 01d0 72175238 bres 21048,#3
1009 ; 304 }
1012 01d4 81 ret
1069 ; 323 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)
1069 ; 324 {
1070 switch .text
1071 01d5 _UART1_IrDAConfig:
1075 ; 325 assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));
1077 ; 327 if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)
1079 01d5 4d tnz a
1080 01d6 2705 jreq L124
1081 ; 329 UART1->CR5 |= UART1_CR5_IRLP;
1083 01d8 72145238 bset 21048,#2
1086 01dc 81 ret
1087 01dd L124:
1088 ; 333 UART1->CR5 &= ((u8)~UART1_CR5_IRLP);
1090 01dd 72155238 bres 21048,#2
1091 ; 335 }
1094 01e1 81 ret
1129 ; 354 void UART1_IrDACmd(FunctionalState NewState)
1129 ; 355 {
1130 switch .text
1131 01e2 _UART1_IrDACmd:
1135 ; 358 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1137 ; 360 if (NewState != DISABLE)
1139 01e2 4d tnz a
1140 01e3 2705 jreq L344
1141 ; 363 UART1->CR5 |= UART1_CR5_IREN;
1143 01e5 72125238 bset 21048,#1
1146 01e9 81 ret
1147 01ea L344:
1148 ; 368 UART1->CR5 &= ((u8)~UART1_CR5_IREN);
1150 01ea 72135238 bres 21048,#1
1151 ; 370 }
1154 01ee 81 ret
1213 ; 388 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
1213 ; 389 {
1214 switch .text
1215 01ef _UART1_LINBreakDetectionConfig:
1219 ; 390 assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));
1221 ; 392 if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)
1223 01ef 4d tnz a
1224 01f0 2705 jreq L574
1225 ; 394 UART1->CR4 |= UART1_CR4_LBDL;
1227 01f2 721a5237 bset 21047,#5
1230 01f6 81 ret
1231 01f7 L574:
1232 ; 398 UART1->CR4 &= ((u8)~UART1_CR4_LBDL);
1234 01f7 721b5237 bres 21047,#5
1235 ; 400 }
1238 01fb 81 ret
1273 ; 418 void UART1_LINCmd(FunctionalState NewState)
1273 ; 419 {
1274 switch .text
1275 01fc _UART1_LINCmd:
1279 ; 420 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1281 ; 422 if (NewState != DISABLE)
1283 01fc 4d tnz a
1284 01fd 2705 jreq L715
1285 ; 425 UART1->CR3 |= UART1_CR3_LINEN;
1287 01ff 721c5236 bset 21046,#6
1290 0203 81 ret
1291 0204 L715:
1292 ; 430 UART1->CR3 &= ((u8)~UART1_CR3_LINEN);
1294 0204 721d5236 bres 21046,#6
1295 ; 432 }
1298 0208 81 ret
1333 ; 451 void UART1_SmartCardCmd(FunctionalState NewState)
1333 ; 452 {
1334 switch .text
1335 0209 _UART1_SmartCardCmd:
1339 ; 453 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1341 ; 455 if (NewState != DISABLE)
1343 0209 4d tnz a
1344 020a 2705 jreq L145
1345 ; 458 UART1->CR5 |= UART1_CR5_SCEN;
1347 020c 721a5238 bset 21048,#5
1350 0210 81 ret
1351 0211 L145:
1352 ; 463 UART1->CR5 &= ((u8)(~UART1_CR5_SCEN));
1354 0211 721b5238 bres 21048,#5
1355 ; 465 }
1358 0215 81 ret
1394 ; 485 void UART1_SmartCardNACKCmd(FunctionalState NewState)
1394 ; 486 {
1395 switch .text
1396 0216 _UART1_SmartCardNACKCmd:
1400 ; 487 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1402 ; 489 if (NewState != DISABLE)
1404 0216 4d tnz a
1405 0217 2705 jreq L365
1406 ; 492 UART1->CR5 |= UART1_CR5_NACK;
1408 0219 72185238 bset 21048,#4
1411 021d 81 ret
1412 021e L365:
1413 ; 497 UART1->CR5 &= ((u8)~(UART1_CR5_NACK));
1415 021e 72195238 bres 21048,#4
1416 ; 499 }
1419 0222 81 ret
1476 ; 518 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)
1476 ; 519 {
1477 switch .text
1478 0223 _UART1_WakeUpConfig:
1482 ; 520 assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));
1484 ; 522 UART1->CR1 &= ((u8)~UART1_CR1_WAKE);
1486 0223 72175234 bres 21044,#3
1487 ; 523 UART1->CR1 |= (u8)UART1_WakeUp;
1489 0227 ca5234 or a,21044
1490 022a c75234 ld 21044,a
1491 ; 524 }
1494 022d 81 ret
1530 ; 541 void UART1_ReceiverWakeUpCmd(FunctionalState NewState)
1530 ; 542 {
1531 switch .text
1532 022e _UART1_ReceiverWakeUpCmd:
1536 ; 543 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1538 ; 545 if (NewState != DISABLE)
1540 022e 4d tnz a
1541 022f 2705 jreq L336
1542 ; 548 UART1->CR2 |= UART1_CR2_RWU;
1544 0231 72125235 bset 21045,#1
1547 0235 81 ret
1548 0236 L336:
1549 ; 553 UART1->CR2 &= ((u8)~UART1_CR2_RWU);
1551 0236 72135235 bres 21045,#1
1552 ; 555 }
1555 023a 81 ret
1578 ; 572 u8 UART1_ReceiveData8(void)
1578 ; 573 {
1579 switch .text
1580 023b _UART1_ReceiveData8:
1584 ; 574 return ((u8)UART1->DR);
1586 023b c65231 ld a,21041
1589 023e 81 ret
1612 ; 593 u16 UART1_ReceiveData9(void)
1612 ; 594 {
1613 switch .text
1614 023f _UART1_ReceiveData9:
1616 023f 89 pushw x
1617 00000002 OFST: set 2
1620 ; 595 return (u16)( (((u16) UART1->DR) | ((u16)(((u16)( (u16)UART1->CR1 & (u16)UART1_CR1_R8)) << 1))) & ((u16)0x01FF));
1622 0240 c65234 ld a,21044
1623 0243 a480 and a,#128
1624 0245 5f clrw x
1625 0246 02 rlwa x,a
1626 0247 58 sllw x
1627 0248 1f01 ldw (OFST-1,sp),x
1628 024a 5f clrw x
1629 024b c65231 ld a,21041
1630 024e 97 ld xl,a
1631 024f 01 rrwa x,a
1632 0250 1a02 or a,(OFST+0,sp)
1633 0252 01 rrwa x,a
1634 0253 1a01 or a,(OFST-1,sp)
1635 0255 a401 and a,#1
1636 0257 01 rrwa x,a
1639 0258 5b02 addw sp,#2
1640 025a 81 ret
1674 ; 615 void UART1_SendData8(u8 Data)
1674 ; 616 {
1675 switch .text
1676 025b _UART1_SendData8:
1680 ; 618 UART1->DR = Data;
1682 025b c75231 ld 21041,a
1683 ; 619 }
1686 025e 81 ret
1720 ; 638 void UART1_SendData9(u16 Data)
1720 ; 639 {
1721 switch .text
1722 025f _UART1_SendData9:
1724 025f 89 pushw x
1725 00000000 OFST: set 0
1728 ; 641 UART1->CR1 &= ((u8)~UART1_CR1_T8);
1730 0260 721d5234 bres 21044,#6
1731 ; 643 UART1->CR1 |= (u8)(((u8)(Data >> 2)) & UART1_CR1_T8);
1733 0264 54 srlw x
1734 0265 54 srlw x
1735 0266 9f ld a,xl
1736 0267 a440 and a,#64
1737 0269 ca5234 or a,21044
1738 026c c75234 ld 21044,a
1739 ; 645 UART1->DR = (u8)(Data);
1741 026f 7b02 ld a,(OFST+2,sp)
1742 0271 c75231 ld 21041,a
1743 ; 646 }
1746 0274 85 popw x
1747 0275 81 ret
1770 ; 662 void UART1_SendBreak(void)
1770 ; 663 {
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