📄 stm8s_uart1.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
58 ; 64 void UART1_DeInit(void)
58 ; 65 {
60 switch .text
61 0000 _UART1_DeInit:
63 00000001 OFST: set 1
66 ; 66 u8 dummy = 0;
68 ; 70 dummy = UART1->SR;
70 0000 c65230 ld a,21040
71 ; 71 dummy = UART1->DR;
73 0003 c65231 ld a,21041
74 ; 73 UART1->BRR2 = UART1_BRR2_RESET_VALUE; /*< Set UART1_BRR2 to reset value 0x00 */
76 0006 725f5233 clr 21043
77 ; 74 UART1->BRR1 = UART1_BRR1_RESET_VALUE; /*< Set UART1_BRR1 to reset value 0x00 */
79 000a 725f5232 clr 21042
80 ; 76 UART1->CR1 = UART1_CR1_RESET_VALUE; /*< Set UART1_CR1 to reset value 0x00 */
82 000e 725f5234 clr 21044
83 ; 77 UART1->CR2 = UART1_CR2_RESET_VALUE; /*< Set UART1_CR2 to reset value 0x00 */
85 0012 725f5235 clr 21045
86 ; 78 UART1->CR3 = UART1_CR3_RESET_VALUE; /*< Set UART1_CR3 to reset value 0x00 */
88 0016 725f5236 clr 21046
89 ; 79 UART1->CR4 = UART1_CR4_RESET_VALUE; /*< Set UART1_CR4 to reset value 0x00 */
91 001a 725f5237 clr 21047
92 ; 80 UART1->CR5 = UART1_CR5_RESET_VALUE; /*< Set UART1_CR5 to reset value 0x00 */
94 001e 725f5238 clr 21048
95 ; 82 UART1->GTR = UART1_GTR_RESET_VALUE;
97 0022 725f5239 clr 21049
98 ; 83 UART1->PSCR = UART1_PSCR_RESET_VALUE;
100 0026 725f523a clr 21050
101 ; 84 }
104 002a 81 ret
407 .const: section .text
408 0000 L41:
409 0000 00000064 dc.l 100
410 ; 104 void UART1_Init(u32 BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
410 ; 105 {
411 switch .text
412 002b _UART1_Init:
414 0000000c OFST: set 12
417 ; 106 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
419 ; 109 assert_param(IS_UART1_BAUDRATE_OK(BaudRate));
421 ; 111 assert_param(IS_UART1_WORDLENGTH_OK(WordLength));
423 ; 113 assert_param(IS_UART1_STOPBITS_OK(StopBits));
425 ; 115 assert_param(IS_UART1_PARITY_OK(Parity));
427 ; 118 assert_param(IS_UART1_MODE_OK((u8)Mode));
429 ; 122 assert_param(IS_UART1_SYNCMODE_OK((u8)SyncMode));
431 ; 124 UART1->CR1 &= (u8)(~UART1_CR1_M); /**< Clear the word length bit */
433 002b 72195234 bres 21044,#4
434 002f 520c subw sp,#12
435 ; 125 UART1->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART1_WordLength value */
437 0031 c65234 ld a,21044
438 0034 1a13 or a,(OFST+7,sp)
439 0036 c75234 ld 21044,a
440 ; 127 UART1->CR3 &= (u8)(~UART1_CR3_STOP); /**< Clear the STOP bits */
442 0039 c65236 ld a,21046
443 003c a4cf and a,#207
444 003e c75236 ld 21046,a
445 ; 128 UART1->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART1_StopBits value */
447 0041 c65236 ld a,21046
448 0044 1a14 or a,(OFST+8,sp)
449 0046 c75236 ld 21046,a
450 ; 130 UART1->CR1 &= (u8)(~(UART1_CR1_PCEN | UART1_CR1_PS )); /**< Clear the Parity Control bit */
452 0049 c65234 ld a,21044
453 004c a4f9 and a,#249
454 004e c75234 ld 21044,a
455 ; 131 UART1->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART1_Parity value */
457 0051 c65234 ld a,21044
458 0054 1a15 or a,(OFST+9,sp)
459 0056 c75234 ld 21044,a
460 ; 133 UART1->BRR1 &= (u8)(~UART1_BRR1_DIVM); /**< Clear the LSB mantissa of UART1DIV */
462 0059 725f5232 clr 21042
463 ; 134 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVM); /**< Clear the MSB mantissa of UART1DIV */
465 005d c65233 ld a,21043
466 0060 a40f and a,#15
467 0062 c75233 ld 21043,a
468 ; 135 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVF); /**< Clear the Fraction bits of UART1DIV */
470 0065 c65233 ld a,21043
471 0068 a4f0 and a,#240
472 006a c75233 ld 21043,a
473 ; 138 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
475 006d 96 ldw x,sp
476 006e 1c000f addw x,#OFST+3
477 0071 cd0000 call c_ltor
479 0074 a604 ld a,#4
480 0076 cd0000 call c_llsh
482 0079 96 ldw x,sp
483 007a 5c incw x
484 007b cd0000 call c_rtol
486 007e cd0000 call _CLK_GetClockFreq
488 0081 96 ldw x,sp
489 0082 5c incw x
490 0083 cd0000 call c_ludv
492 0086 96 ldw x,sp
493 0087 1c0009 addw x,#OFST-3
494 008a cd0000 call c_rtol
496 ; 139 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
498 008d 96 ldw x,sp
499 008e 1c000f addw x,#OFST+3
500 0091 cd0000 call c_ltor
502 0094 a604 ld a,#4
503 0096 cd0000 call c_llsh
505 0099 96 ldw x,sp
506 009a 5c incw x
507 009b cd0000 call c_rtol
509 009e cd0000 call _CLK_GetClockFreq
511 00a1 a664 ld a,#100
512 00a3 cd0000 call c_smul
514 00a6 96 ldw x,sp
515 00a7 5c incw x
516 00a8 cd0000 call c_ludv
518 00ab 96 ldw x,sp
519 00ac 1c0005 addw x,#OFST-7
520 00af cd0000 call c_rtol
522 ; 140 UART1->BRR2 |= (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (u8)0x0F); /**< Set the fraction of UART1DIV */
524 00b2 96 ldw x,sp
525 00b3 1c0009 addw x,#OFST-3
526 00b6 cd0000 call c_ltor
528 00b9 a664 ld a,#100
529 00bb cd0000 call c_smul
531 00be 96 ldw x,sp
532 00bf 5c incw x
533 00c0 cd0000 call c_rtol
535 00c3 96 ldw x,sp
536 00c4 1c0005 addw x,#OFST-7
537 00c7 cd0000 call c_ltor
539 00ca 96 ldw x,sp
540 00cb 5c incw x
541 00cc cd0000 call c_lsub
543 00cf a604 ld a,#4
544 00d1 cd0000 call c_llsh
546 00d4 ae0000 ldw x,#L41
547 00d7 cd0000 call c_ludv
549 00da b603 ld a,c_lreg+3
550 00dc a40f and a,#15
551 00de ca5233 or a,21043
552 00e1 c75233 ld 21043,a
553 ; 141 UART1->BRR2 |= (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0); /**< Set the MSB mantissa of UART1DIV */
555 00e4 96 ldw x,sp
556 00e5 1c0009 addw x,#OFST-3
557 00e8 cd0000 call c_ltor
559 00eb a604 ld a,#4
560 00ed cd0000 call c_lursh
562 00f0 b603 ld a,c_lreg+3
563 00f2 a4f0 and a,#240
564 00f4 b703 ld c_lreg+3,a
565 00f6 3f02 clr c_lreg+2
566 00f8 3f01 clr c_lreg+1
567 00fa 3f00 clr c_lreg
568 00fc ca5233 or a,21043
569 00ff c75233 ld 21043,a
570 ; 142 UART1->BRR1 |= (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UART1DIV */
572 0102 c65232 ld a,21042
573 0105 1a0c or a,(OFST+0,sp)
574 0107 c75232 ld 21042,a
575 ; 144 UART1->CR2 &= (u8)~(UART1_CR2_TEN | UART1_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
577 010a c65235 ld a,21045
578 010d a4f3 and a,#243
579 010f c75235 ld 21045,a
580 ; 145 UART1->CR3 &= (u8)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
582 0112 c65236 ld a,21046
583 0115 a4f8 and a,#248
584 0117 c75236 ld 21046,a
585 ; 146 UART1->CR3 |= (u8)((u8)SyncMode & (u8)(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
587 011a 7b16 ld a,(OFST+10,sp)
588 011c a407 and a,#7
589 011e ca5236 or a,21046
590 0121 c75236 ld 21046,a
591 ; 148 if ((u8)Mode & (u8)UART1_MODE_TX_ENABLE)
593 0124 7b17 ld a,(OFST+11,sp)
594 0126 a504 bcp a,#4
595 0128 2706 jreq L102
596 ; 150 UART1->CR2 |= (u8)UART1_CR2_TEN; /**< Set the Transmitter Enable bit */
598 012a 72165235 bset 21045,#3
600 012e 2004 jra L302
601 0130 L102:
602 ; 154 UART1->CR2 &= (u8)(~UART1_CR2_TEN); /**< Clear the Transmitter Disable bit */
604 0130 72175235 bres 21045,#3
605 0134 L302:
606 ; 156 if ((u8)Mode & (u8)UART1_MODE_RX_ENABLE)
608 0134 a508 bcp a,#8
609 0136 2706 jreq L502
610 ; 158 UART1->CR2 |= (u8)UART1_CR2_REN; /**< Set the Receiver Enable bit */
612 0138 72145235 bset 21045,#2
614 013c 2004 jra L702
615 013e L502:
616 ; 162 UART1->CR2 &= (u8)(~UART1_CR2_REN); /**< Clear the Receiver Disable bit */
618 013e 72155235 bres 21045,#2
619 0142 L702:
620 ; 165 if ((u8)SyncMode&(u8)UART1_SYNCMODE_CLOCK_DISABLE)
622 0142 7b16 ld a,(OFST+10,sp)
623 0144 2a06 jrpl L112
624 ; 167 UART1->CR3 &= (u8)(~UART1_CR3_CKEN); /**< Clear the Clock Enable bit */
626 0146 72175236 bres 21046,#3
628 014a 2008 jra L312
629 014c L112:
630 ; 172 UART1->CR3 |= (u8)((u8)SyncMode & UART1_CR3_CKEN);
632 014c a408 and a,#8
633 014e ca5236 or a,21046
634 0151 c75236 ld 21046,a
635 0154 L312:
636 ; 174 }
639 0154 5b0c addw sp,#12
640 0156 81 ret
695 ; 195 void UART1_Cmd(FunctionalState NewState)
695 ; 196 {
696 switch .text
697 0157 _UART1_Cmd:
701 ; 197 if (NewState != DISABLE)
703 0157 4d tnz a
704 0158 2705 jreq L342
705 ; 199 UART1->CR1 &= (u8)(~UART1_CR1_UARTD); /**< UART1 Enable */
707 015a 721b5234 bres 21044,#5
710 015e 81 ret
711 015f L342:
712 ; 203 UART1->CR1 |= UART1_CR1_UARTD; /**< UART1 Disable (for low power consumption) */
714 015f 721a5234 bset 21044,#5
715 ; 205 }
718 0163 81 ret
843 ; 231 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
843 ; 232 {
844 switch .text
845 0164 _UART1_ITConfig:
847 0164 89 pushw x
848 0165 89 pushw x
849 00000002 OFST: set 2
852 ; 233 u8 uartreg, itpos = 0x00;
854 ; 234 assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));
856 ; 235 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
858 ; 238 uartreg = (u8)(UART1_IT >> (u8)0x08);
860 0166 9e ld a,xh
861 0167 6b01 ld (OFST-1,sp),a
862 ; 240 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
864 0169 9f ld a,xl
865 016a a40f and a,#15
866 016c 5f clrw x
867 016d 97 ld xl,a
868 016e a601 ld a,#1
869 0170 5d tnzw x
870 0171 2704 jreq L22
871 0173 L42:
872 0173 48 sll a
873 0174 5a decw x
874 0175 26fc jrne L42
875 0177 L22:
876 0177 6b02 ld (OFST+0,sp),a
877 ; 242 if (NewState != DISABLE)
879 0179 7b07 ld a,(OFST+5,sp)
880 017b 271f jreq L523
881 ; 245 if (uartreg == 0x01)
883 017d 7b01 ld a,(OFST-1,sp)
884 017f a101 cp a,#1
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