📄 stm8s_tim3.ls
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2106 ; 830 }
2109 0205 81 ret
2154 ; 852 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
2154 ; 853 {
2155 switch .text
2156 0206 _TIM3_CCxCmd:
2158 0206 89 pushw x
2159 00000000 OFST: set 0
2162 ; 855 assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
2164 ; 856 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2166 ; 858 if (TIM3_Channel == TIM3_CHANNEL_1)
2168 0207 9e ld a,xh
2169 0208 4d tnz a
2170 0209 2610 jrne L3311
2171 ; 861 if (NewState != DISABLE)
2173 020b 9f ld a,xl
2174 020c 4d tnz a
2175 020d 2706 jreq L5311
2176 ; 863 TIM3->CCER1 |= TIM3_CCER1_CC1E;
2178 020f 72105327 bset 21287,#0
2180 0213 2014 jra L1411
2181 0215 L5311:
2182 ; 867 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
2184 0215 72115327 bres 21287,#0
2185 0219 200e jra L1411
2186 021b L3311:
2187 ; 874 if (NewState != DISABLE)
2189 021b 7b02 ld a,(OFST+2,sp)
2190 021d 2706 jreq L3411
2191 ; 876 TIM3->CCER1 |= TIM3_CCER1_CC2E;
2193 021f 72185327 bset 21287,#4
2195 0223 2004 jra L1411
2196 0225 L3411:
2197 ; 880 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
2199 0225 72195327 bres 21287,#4
2200 0229 L1411:
2201 ; 884 }
2204 0229 85 popw x
2205 022a 81 ret
2250 ; 914 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
2250 ; 915 {
2251 switch .text
2252 022b _TIM3_SelectOCxM:
2254 022b 89 pushw x
2255 00000000 OFST: set 0
2258 ; 917 assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
2260 ; 918 assert_param(IS_TIM3_OCM_OK(TIM3_OCMode));
2262 ; 920 if (TIM3_Channel == TIM3_CHANNEL_1)
2264 022c 9e ld a,xh
2265 022d 4d tnz a
2266 022e 2610 jrne L1711
2267 ; 923 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
2269 0230 72115327 bres 21287,#0
2270 ; 926 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_OCMode);
2272 0234 c65325 ld a,21285
2273 0237 a48f and a,#143
2274 0239 1a02 or a,(OFST+2,sp)
2275 023b c75325 ld 21285,a
2277 023e 200e jra L3711
2278 0240 L1711:
2279 ; 931 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
2281 0240 72195327 bres 21287,#4
2282 ; 934 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_OCMode);
2284 0244 c65326 ld a,21286
2285 0247 a48f and a,#143
2286 0249 1a02 or a,(OFST+2,sp)
2287 024b c75326 ld 21286,a
2288 024e L3711:
2289 ; 936 }
2292 024e 85 popw x
2293 024f 81 ret
2327 ; 954 void TIM3_SetCounter(u16 Counter)
2327 ; 955 {
2328 switch .text
2329 0250 _TIM3_SetCounter:
2333 ; 957 TIM3->CNTRH = (u8)(Counter >> 8);
2335 0250 9e ld a,xh
2336 0251 c75328 ld 21288,a
2337 ; 958 TIM3->CNTRL = (u8)(Counter);
2339 0254 9f ld a,xl
2340 0255 c75329 ld 21289,a
2341 ; 960 }
2344 0258 81 ret
2378 ; 978 void TIM3_SetAutoreload(u16 Autoreload)
2378 ; 979 {
2379 switch .text
2380 0259 _TIM3_SetAutoreload:
2384 ; 981 TIM3->ARRH = (u8)(Autoreload >> 8);
2386 0259 9e ld a,xh
2387 025a c7532b ld 21291,a
2388 ; 982 TIM3->ARRL = (u8)(Autoreload);
2390 025d 9f ld a,xl
2391 025e c7532c ld 21292,a
2392 ; 983 }
2395 0261 81 ret
2429 ; 1001 void TIM3_SetCompare1(u16 Compare1)
2429 ; 1002 {
2430 switch .text
2431 0262 _TIM3_SetCompare1:
2435 ; 1004 TIM3->CCR1H = (u8)(Compare1 >> 8);
2437 0262 9e ld a,xh
2438 0263 c7532d ld 21293,a
2439 ; 1005 TIM3->CCR1L = (u8)(Compare1);
2441 0266 9f ld a,xl
2442 0267 c7532e ld 21294,a
2443 ; 1006 }
2446 026a 81 ret
2480 ; 1024 void TIM3_SetCompare2(u16 Compare2)
2480 ; 1025 {
2481 switch .text
2482 026b _TIM3_SetCompare2:
2486 ; 1027 TIM3->CCR2H = (u8)(Compare2 >> 8);
2488 026b 9e ld a,xh
2489 026c c7532f ld 21295,a
2490 ; 1028 TIM3->CCR2L = (u8)(Compare2);
2492 026f 9f ld a,xl
2493 0270 c75330 ld 21296,a
2494 ; 1029 }
2497 0273 81 ret
2533 ; 1051 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
2533 ; 1052 {
2534 switch .text
2535 0274 _TIM3_SetIC1Prescaler:
2537 0274 88 push a
2538 00000000 OFST: set 0
2541 ; 1054 assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC1Prescaler));
2543 ; 1057 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_ICxPSC)) | (u8)TIM3_IC1Prescaler);
2545 0275 c65325 ld a,21285
2546 0278 a4f3 and a,#243
2547 027a 1a01 or a,(OFST+1,sp)
2548 027c c75325 ld 21285,a
2549 ; 1058 }
2552 027f 84 pop a
2553 0280 81 ret
2589 ; 1079 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
2589 ; 1080 {
2590 switch .text
2591 0281 _TIM3_SetIC2Prescaler:
2593 0281 88 push a
2594 00000000 OFST: set 0
2597 ; 1082 assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC2Prescaler));
2599 ; 1085 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_ICxPSC)) | (u8)TIM3_IC2Prescaler);
2601 0282 c65326 ld a,21286
2602 0285 a4f3 and a,#243
2603 0287 1a01 or a,(OFST+1,sp)
2604 0289 c75326 ld 21286,a
2605 ; 1086 }
2608 028c 84 pop a
2609 028d 81 ret
2661 ; 1103 u16 TIM3_GetCapture1(void)
2661 ; 1104 {
2662 switch .text
2663 028e _TIM3_GetCapture1:
2665 028e 5204 subw sp,#4
2666 00000004 OFST: set 4
2669 ; 1106 u16 tmpccr1 = 0;
2671 ; 1107 u8 tmpccr1l=0, tmpccr1h=0;
2675 ; 1109 tmpccr1h = TIM3->CCR1H;
2677 0290 c6532d ld a,21293
2678 0293 6b02 ld (OFST-2,sp),a
2679 ; 1110 tmpccr1l = TIM3->CCR1L;
2681 0295 c6532e ld a,21294
2682 0298 6b01 ld (OFST-3,sp),a
2683 ; 1112 tmpccr1 = (u16)(tmpccr1l);
2685 029a 5f clrw x
2686 029b 97 ld xl,a
2687 029c 1f03 ldw (OFST-1,sp),x
2688 ; 1113 tmpccr1 |= (u16)((u16)tmpccr1h << 8);
2690 029e 5f clrw x
2691 029f 7b02 ld a,(OFST-2,sp)
2692 02a1 97 ld xl,a
2693 02a2 7b04 ld a,(OFST+0,sp)
2694 02a4 01 rrwa x,a
2695 02a5 1a03 or a,(OFST-1,sp)
2696 02a7 01 rrwa x,a
2697 ; 1115 return (u16)tmpccr1;
2701 02a8 5b04 addw sp,#4
2702 02aa 81 ret
2754 ; 1134 u16 TIM3_GetCapture2(void)
2754 ; 1135 {
2755 switch .text
2756 02ab _TIM3_GetCapture2:
2758 02ab 5204 subw sp,#4
2759 00000004 OFST: set 4
2762 ; 1137 u16 tmpccr2 = 0;
2764 ; 1138 u8 tmpccr2l=0, tmpccr2h=0;
2768 ; 1140 tmpccr2h = TIM3->CCR2H;
2770 02ad c6532f ld a,21295
2771 02b0 6b02 ld (OFST-2,sp),a
2772 ; 1141 tmpccr2l = TIM3->CCR2L;
2774 02b2 c65330 ld a,21296
2775 02b5 6b01 ld (OFST-3,sp),a
2776 ; 1143 tmpccr2 = (u16)(tmpccr2l);
2778 02b7 5f clrw x
2779 02b8 97 ld xl,a
2780 02b9 1f03 ldw (OFST-1,sp),x
2781 ; 1144 tmpccr2 |= (u16)((u16)tmpccr2h << 8);
2783 02bb 5f clrw x
2784 02bc 7b02 ld a,(OFST-2,sp)
2785 02be 97 ld xl,a
2786 02bf 7b04 ld a,(OFST+0,sp)
2787 02c1 01 rrwa x,a
2788 02c2 1a03 or a,(OFST-1,sp)
2789 02c4 01 rrwa x,a
2790 ; 1146 return (u16)tmpccr2;
2794 02c5 5b04 addw sp,#4
2795 02c7 81 ret
2818 ; 1165 u16 TIM3_GetCounter(void)
2818 ; 1166 {
2819 switch .text
2820 02c8 _TIM3_GetCounter:
2822 02c8 89 pushw x
2823 00000002 OFST: set 2
2826 ; 1168 return (u16)(((u16)TIM3->CNTRH << 8) | (u16)(TIM3->CNTRL));
2828 02c9 c65329 ld a,21289
2829 02cc 5f clrw x
2830 02cd 97 ld xl,a
2831 02ce 1f01 ldw (OFST-1,sp),x
2832 02d0 5f clrw x
2833 02d1 c65328 ld a,21288
2834 02d4 97 ld xl,a
2835 02d5 7b02 ld a,(OFST+0,sp)
2836 02d7 01 rrwa x,a
2837 02d8 1a01 or a,(OFST-1,sp)
2838 02da 01 rrwa x,a
2841 02db 5b02 addw sp,#2
2842 02dd 81 ret
2866 ; 1188 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)
2866 ; 1189 {
2867 switch .text
2868 02de _TIM3_GetPrescaler:
2872 ; 1191 return (TIM3_Prescaler_TypeDef)(TIM3->PSCR);
2874 02de c6532a ld a,21290
2877 02e1 81 ret
3002 ; 1216 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)
3002 ; 1217 {
3003 switch .text
3004 02e2 _TIM3_GetFlagStatus:
3006 02e2 5203 subw sp,#3
3007 00000003 OFST: set 3
3010 ; 1218 FlagStatus bitstatus = RESET;
3012 ; 1222 assert_param(IS_TIM3_GET_FLAG_OK(TIM3_FLAG));
3014 ; 1224 tim3_flag_l = (u8)(TIM3_FLAG);
3016 02e4 9f ld a,xl
3017 02e5 6b02 ld (OFST-1,sp),a
3018 ; 1225 tim3_flag_h = (u8)(TIM3_FLAG >> 8);
3020 02e7 9e ld a,xh
3021 02e8 6b03 ld (OFST+0,sp),a
3022 ; 1227 if (((TIM3->SR1 & tim3_flag_l) | (TIM3->SR2 & tim3_flag_h)) != (u8)RESET )
3024 02ea c45323 and a,21283
3025 02ed 6b01 ld (OFST-2,sp),a
3026 02ef c65322 ld a,21282
3027 02f2 1402 and a,(OFST-1,sp)
3028 02f4 1a01 or a,(OFST-2,sp)
3029 02f6 2702 jreq L5741
3030 ; 1229 bitstatus = SET;
3032 02f8 a601 ld a,#1
3034 02fa L5741:
3035 ; 1233 bitstatus = RESET;
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