📄 stm8s_tim3.ls
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1040 0121 95 ld xh,a
1041 0122 cd035e call L5_TI2_Config
1043 0125 84 pop a
1044 ; 344 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1046 0126 7b08 ld a,(OFST+6,sp)
1047 0128 cd0281 call _TIM3_SetIC2Prescaler
1050 012b 2024 jra L724
1051 012d L524:
1052 ; 349 TI2_Config(TIM3_ICPolarity, TIM3_ICSelection,
1052 ; 350 TIM3_ICFilter);
1054 012d 7b09 ld a,(OFST+7,sp)
1055 012f 88 push a
1056 0130 7b08 ld a,(OFST+6,sp)
1057 0132 97 ld xl,a
1058 0133 7b05 ld a,(OFST+3,sp)
1059 0135 95 ld xh,a
1060 0136 cd035e call L5_TI2_Config
1062 0139 84 pop a
1063 ; 353 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1065 013a 7b08 ld a,(OFST+6,sp)
1066 013c cd0281 call _TIM3_SetIC2Prescaler
1068 ; 356 TI1_Config(icpolarity, icselection, TIM3_ICFilter);
1070 013f 7b09 ld a,(OFST+7,sp)
1071 0141 88 push a
1072 0142 7b03 ld a,(OFST+1,sp)
1073 0144 97 ld xl,a
1074 0145 7b02 ld a,(OFST+0,sp)
1075 0147 95 ld xh,a
1076 0148 cd032e call L3_TI1_Config
1078 014b 84 pop a
1079 ; 359 TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
1081 014c 7b08 ld a,(OFST+6,sp)
1082 014e cd0274 call _TIM3_SetIC1Prescaler
1084 0151 L724:
1085 ; 361 }
1088 0151 5b04 addw sp,#4
1089 0153 81 ret
1144 ; 379 void TIM3_Cmd(FunctionalState NewState)
1144 ; 380 {
1145 switch .text
1146 0154 _TIM3_Cmd:
1150 ; 382 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1152 ; 385 if (NewState != DISABLE)
1154 0154 4d tnz a
1155 0155 2705 jreq L754
1156 ; 387 TIM3->CR1 |= TIM3_CR1_CEN;
1158 0157 72105320 bset 21280,#0
1161 015b 81 ret
1162 015c L754:
1163 ; 391 TIM3->CR1 &= (u8)(~TIM3_CR1_CEN);
1165 015c 72115320 bres 21280,#0
1166 ; 393 }
1169 0160 81 ret
1241 ; 417 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
1241 ; 418 {
1242 switch .text
1243 0161 _TIM3_ITConfig:
1245 0161 89 pushw x
1246 00000000 OFST: set 0
1249 ; 420 assert_param(IS_TIM3_IT_OK(TIM3_IT));
1251 ; 421 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1253 ; 423 if (NewState != DISABLE)
1255 0162 9f ld a,xl
1256 0163 4d tnz a
1257 0164 2706 jreq L715
1258 ; 426 TIM3->IER |= TIM3_IT;
1260 0166 9e ld a,xh
1261 0167 ca5321 or a,21281
1263 016a 2006 jra L125
1264 016c L715:
1265 ; 431 TIM3->IER &= (u8)(~TIM3_IT);
1267 016c 7b01 ld a,(OFST+1,sp)
1268 016e 43 cpl a
1269 016f c45321 and a,21281
1270 0172 L125:
1271 0172 c75321 ld 21281,a
1272 ; 433 }
1275 0175 85 popw x
1276 0176 81 ret
1312 ; 451 void TIM3_UpdateDisableConfig(FunctionalState NewState)
1312 ; 452 {
1313 switch .text
1314 0177 _TIM3_UpdateDisableConfig:
1318 ; 454 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1320 ; 457 if (NewState != DISABLE)
1322 0177 4d tnz a
1323 0178 2705 jreq L145
1324 ; 459 TIM3->CR1 |= TIM3_CR1_UDIS;
1326 017a 72125320 bset 21280,#1
1329 017e 81 ret
1330 017f L145:
1331 ; 463 TIM3->CR1 &= (u8)(~TIM3_CR1_UDIS);
1333 017f 72135320 bres 21280,#1
1334 ; 465 }
1337 0183 81 ret
1395 ; 484 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
1395 ; 485 {
1396 switch .text
1397 0184 _TIM3_UpdateRequestConfig:
1401 ; 487 assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
1403 ; 490 if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
1405 0184 4d tnz a
1406 0185 2705 jreq L375
1407 ; 492 TIM3->CR1 |= TIM3_CR1_URS;
1409 0187 72145320 bset 21280,#2
1412 018b 81 ret
1413 018c L375:
1414 ; 496 TIM3->CR1 &= (u8)(~TIM3_CR1_URS);
1416 018c 72155320 bres 21280,#2
1417 ; 498 }
1420 0190 81 ret
1477 ; 518 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
1477 ; 519 {
1478 switch .text
1479 0191 _TIM3_SelectOnePulseMode:
1483 ; 521 assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
1485 ; 524 if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
1487 0191 4d tnz a
1488 0192 2705 jreq L526
1489 ; 526 TIM3->CR1 |= TIM3_CR1_OPM;
1491 0194 72165320 bset 21280,#3
1494 0198 81 ret
1495 0199 L526:
1496 ; 530 TIM3->CR1 &= (u8)(~TIM3_CR1_OPM);
1498 0199 72175320 bres 21280,#3
1499 ; 533 }
1502 019d 81 ret
1570 ; 573 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
1570 ; 574 TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
1570 ; 575 {
1571 switch .text
1572 019e _TIM3_PrescalerConfig:
1576 ; 577 assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
1578 ; 578 assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
1580 ; 581 TIM3->PSCR = Prescaler;
1582 019e 9e ld a,xh
1583 019f c7532a ld 21290,a
1584 ; 584 TIM3->EGR = TIM3_PSCReloadMode;
1586 01a2 9f ld a,xl
1587 01a3 c75324 ld 21284,a
1588 ; 585 }
1591 01a6 81 ret
1649 ; 605 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1649 ; 606 {
1650 switch .text
1651 01a7 _TIM3_ForcedOC1Config:
1653 01a7 88 push a
1654 00000000 OFST: set 0
1657 ; 608 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1659 ; 611 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1661 01a8 c65325 ld a,21285
1662 01ab a48f and a,#143
1663 01ad 1a01 or a,(OFST+1,sp)
1664 01af c75325 ld 21285,a
1665 ; 612 }
1668 01b2 84 pop a
1669 01b3 81 ret
1705 ; 632 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1705 ; 633 {
1706 switch .text
1707 01b4 _TIM3_ForcedOC2Config:
1709 01b4 88 push a
1710 00000000 OFST: set 0
1713 ; 635 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1715 ; 638 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1717 01b5 c65326 ld a,21286
1718 01b8 a48f and a,#143
1719 01ba 1a01 or a,(OFST+1,sp)
1720 01bc c75326 ld 21286,a
1721 ; 639 }
1724 01bf 84 pop a
1725 01c0 81 ret
1761 ; 657 void TIM3_ARRPreloadConfig(FunctionalState NewState)
1761 ; 658 {
1762 switch .text
1763 01c1 _TIM3_ARRPreloadConfig:
1767 ; 660 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1769 ; 663 if (NewState != DISABLE)
1771 01c1 4d tnz a
1772 01c2 2705 jreq L547
1773 ; 665 TIM3->CR1 |= TIM3_CR1_ARPE;
1775 01c4 721e5320 bset 21280,#7
1778 01c8 81 ret
1779 01c9 L547:
1780 ; 669 TIM3->CR1 &= (u8)(~TIM3_CR1_ARPE);
1782 01c9 721f5320 bres 21280,#7
1783 ; 671 }
1786 01cd 81 ret
1822 ; 689 void TIM3_OC1PreloadConfig(FunctionalState NewState)
1822 ; 690 {
1823 switch .text
1824 01ce _TIM3_OC1PreloadConfig:
1828 ; 692 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1830 ; 695 if (NewState != DISABLE)
1832 01ce 4d tnz a
1833 01cf 2705 jreq L767
1834 ; 697 TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
1836 01d1 72165325 bset 21285,#3
1839 01d5 81 ret
1840 01d6 L767:
1841 ; 701 TIM3->CCMR1 &= (u8)(~TIM3_CCMR_OCxPE);
1843 01d6 72175325 bres 21285,#3
1844 ; 703 }
1847 01da 81 ret
1883 ; 721 void TIM3_OC2PreloadConfig(FunctionalState NewState)
1883 ; 722 {
1884 switch .text
1885 01db _TIM3_OC2PreloadConfig:
1889 ; 724 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1891 ; 727 if (NewState != DISABLE)
1893 01db 4d tnz a
1894 01dc 2705 jreq L1101
1895 ; 729 TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
1897 01de 72165326 bset 21286,#3
1900 01e2 81 ret
1901 01e3 L1101:
1902 ; 733 TIM3->CCMR2 &= (u8)(~TIM3_CCMR_OCxPE);
1904 01e3 72175326 bres 21286,#3
1905 ; 735 }
1908 01e7 81 ret
1973 ; 755 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
1973 ; 756 {
1974 switch .text
1975 01e8 _TIM3_GenerateEvent:
1979 ; 758 assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
1981 ; 761 TIM3->EGR = TIM3_EventSource;
1983 01e8 c75324 ld 21284,a
1984 ; 762 }
1987 01eb 81 ret
2023 ; 782 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2023 ; 783 {
2024 switch .text
2025 01ec _TIM3_OC1PolarityConfig:
2029 ; 785 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2031 ; 788 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2033 01ec 4d tnz a
2034 01ed 2705 jreq L3601
2035 ; 790 TIM3->CCER1 |= TIM3_CCER1_CC1P;
2037 01ef 72125327 bset 21287,#1
2040 01f3 81 ret
2041 01f4 L3601:
2042 ; 794 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
2044 01f4 72135327 bres 21287,#1
2045 ; 796 }
2048 01f8 81 ret
2084 ; 816 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2084 ; 817 {
2085 switch .text
2086 01f9 _TIM3_OC2PolarityConfig:
2090 ; 819 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2092 ; 822 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2094 01f9 4d tnz a
2095 01fa 2705 jreq L5011
2096 ; 824 TIM3->CCER1 |= TIM3_CCER1_CC2P;
2098 01fc 721a5327 bset 21287,#5
2101 0200 81 ret
2102 0201 L5011:
2103 ; 828 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
2105 0201 721b5327 bres 21287,#5
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