📄 mc_stm8s_bldc_drive.ls
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2983 042c L1011:
2984 ; 1497 case ADC_TEMP_SAMPLE:
2984 ; 1498 ADC_Buffer[ ADC_TEMP_INDEX ] = data;
2986 042c bf3b ldw _ADC_Buffer+6,x
2987 ; 1499 ADC_Async_State = ADC_NEUTRAL_POINT_INIT;
2989 042e a604 ld a,#4
2990 ; 1500 break;
2992 0430 200a jp LC002
2993 0432 L3011:
2994 ; 1502 case ADC_NEUTRAL_POINT_SAMPLE:
2994 ; 1503 ADC_Buffer[ ADC_NEUTRAL_POINT_INDEX ] = data;
2996 0432 bf3d ldw _ADC_Buffer+8,x
2997 ; 1504 ADC_Async_State = ADC_USER_ASYNC_INIT;
2999 0434 a606 ld a,#6
3000 ; 1505 break;
3002 0436 2004 jp LC002
3003 0438 L5011:
3004 ; 1507 case ADC_USER_ASYNC_SAMPLE:
3004 ; 1508 ADC_Buffer[ ADC_USER_ASYNC_INDEX ] = data;
3006 0438 bf3f ldw _ADC_Buffer+10,x
3007 ; 1509 ADC_Async_State = ADC_CURRENT_INIT; //ADC_BUS_INIT;
3009 043a a612 ld a,#18
3010 043c LC002:
3011 043c b708 ld _ADC_Async_State,a
3012 ; 1510 break;
3014 043e L1411:
3015 ; 1514 switch (ADC_Async_State)
3017 043e b608 ld a,_ADC_Async_State
3019 ; 1544 break;
3020 0440 2719 jreq L1111
3021 0442 a002 sub a,#2
3022 0444 271f jreq L3111
3023 0446 a002 sub a,#2
3024 0448 2725 jreq L5111
3025 044a a002 sub a,#2
3026 044c 272b jreq L7111
3027 ; 1516 default:
3027 ; 1517
3027 ; 1518
3027 ; 1519 case ADC_CURRENT_INIT:
3027 ; 1520 ADC2->CSR = (ADC_CURRENT_CHANNEL|BIT5);
3029 044e 35215400 mov 21504,#33
3030 ; 1521 ADC_Async_State = ADC_CURRENT_SAMPLE;
3032 0452 35130008 mov _ADC_Async_State,#19
3033 ; 1522 SetSamplingPoint_Current();
3035 0456 cd0c2d call _SetSamplingPoint_Current
3037 ; 1523 break;
3039 0459 2026 jra L5411
3040 045b L1111:
3041 ; 1526 case ADC_BUS_INIT:
3041 ; 1527 ADC2->CSR = (ADC_BUS_CHANNEL|BIT5);
3043 045b 35205400 mov 21504,#32
3044 ; 1528 ADC_Async_State = ADC_BUS_SAMPLE;
3046 045f 35010008 mov _ADC_Async_State,#1
3047 ; 1529 break;
3049 0463 201c jra L5411
3050 0465 L3111:
3051 ; 1531 case ADC_TEMP_INIT:
3051 ; 1532 ADC2->CSR = (ADC_TEMP_CHANNEL|BIT5);
3053 0465 35225400 mov 21504,#34
3054 ; 1533 ADC_Async_State = ADC_TEMP_SAMPLE;
3056 0469 35030008 mov _ADC_Async_State,#3
3057 ; 1534 break;
3059 046d 2012 jra L5411
3060 046f L5111:
3061 ; 1536 case ADC_NEUTRAL_POINT_INIT:
3061 ; 1537 ADC2->CSR = (ADC_NEUTRAL_POINT_CHANNEL|BIT5);
3063 046f 35225400 mov 21504,#34
3064 ; 1538 ADC_Async_State = ADC_NEUTRAL_POINT_SAMPLE;
3066 0473 35050008 mov _ADC_Async_State,#5
3067 ; 1539 break;
3069 0477 2008 jra L5411
3070 0479 L7111:
3071 ; 1541 case ADC_USER_ASYNC_INIT:
3071 ; 1542 ADC2->CSR = (ADC_USER_ASYNC_CHANNEL|BIT5);
3073 0479 35245400 mov 21504,#36
3074 ; 1543 ADC_Async_State = ADC_USER_ASYNC_SAMPLE;
3076 047d 35070008 mov _ADC_Async_State,#7
3077 ; 1544 break;
3079 0481 L5411:
3080 ; 1550 ADC2->CR2 |= BIT6;
3082 0481 721c5402 bset 21506,#6
3083 ; 1552 ADC2->CR1 |= BIT0;
3085 ; 1557 }
3088 0485 5b02 addw sp,#2
3089 0487 72105401 bset 21505,#0
3090 048b 85 popw x
3091 048c bf00 ldw c_lreg,x
3092 048e 85 popw x
3093 048f bf02 ldw c_lreg+2,x
3094 0491 85 popw x
3095 0492 bf00 ldw c_y,x
3096 0494 320002 pop c_y+2
3097 0497 85 popw x
3098 0498 bf00 ldw c_x,x
3099 049a 320002 pop c_x+2
3100 049d 80 iret
3123 ; 1560 void DebugPinsOff(void)
3123 ; 1561 {
3124 switch .text
3125 049e _DebugPinsOff:
3129 ; 1568 }
3132 049e 81 ret
3158 ; 1572 void Init_TIM1(void)
3158 ; 1573 {
3159 switch .text
3160 049f _Init_TIM1:
3164 ; 1575 TIM1->CR1 = BIT2;
3166 049f 35045250 mov 21072,#4
3167 ; 1578 TIM1->CR2 = (BIT6|BIT5|BIT4|BIT0);
3169 04a3 35715251 mov 21073,#113
3170 ; 1581 TIM1->SMCR = 0;
3172 04a7 725f5252 clr 21074
3173 ; 1585 TIM1->ETR = CURRENT_FILTER;
3175 04ab 725f5253 clr 21075
3176 ; 1589 TIM1->IER = 0;
3178 04af 725f5254 clr 21076
3179 ; 1591 TIM1->CCER1 = 0;
3181 04b3 725f525c clr 21084
3182 ; 1592 TIM1->CCER2 = 0;
3184 04b7 725f525d clr 21085
3185 ; 1595 TIM1->CCMR1 = CCMR_PWM;
3187 04bb 35e85258 mov 21080,#232
3188 ; 1597 TIM1->CCMR2 = CCMR_PWM;
3190 04bf 35e85259 mov 21081,#232
3191 ; 1599 TIM1->CCMR3 = CCMR_PWM;
3193 04c3 35e8525a mov 21082,#232
3194 ; 1602 TIM1->CCMR4 = BIT6|BIT5|BIT4|BIT3;
3196 04c7 3578525b mov 21083,#120
3197 ; 1605 TIM1->PSCRH = 0;
3199 04cb 725f5260 clr 21088
3200 ; 1606 TIM1->PSCRL = 0;
3202 04cf 725f5261 clr 21089
3203 ; 1608 ToCMPxH( TIM1->ARRH, hArrPwmVal );
3205 04d3 35035262 mov 21090,#3
3206 ; 1609 ToCMPxL( TIM1->ARRL, hArrPwmVal );
3208 04d7 35785263 mov 21091,#120
3209 ; 1612 TIM1->RCR = 0;
3211 04db 725f5264 clr 21092
3212 ; 1615 ToCMPxH( TIM1->CCR1H, 0 );
3214 04df 725f5265 clr 21093
3215 ; 1616 ToCMPxL( TIM1->CCR1L, 0 );
3217 04e3 725f5266 clr 21094
3218 ; 1618 ToCMPxH( TIM1->CCR2H, 0 );
3220 04e7 725f5267 clr 21095
3221 ; 1619 ToCMPxL( TIM1->CCR2L, 0 );
3223 04eb 725f5268 clr 21096
3224 ; 1621 ToCMPxH( TIM1->CCR3H, 0 );
3226 04ef 725f5269 clr 21097
3227 ; 1622 ToCMPxL( TIM1->CCR3L, 0 );
3229 04f3 725f526a clr 21098
3230 ; 1629 ToCMPxH( TIM1->CCR4H, hArrPwmVal - MILLIAMP_TOCNT (STARTUP_CURRENT_LIMITATION) );
3232 04f7 35f1526b mov 21099,#241
3233 ; 1630 ToCMPxL( TIM1->CCR4L, hArrPwmVal - MILLIAMP_TOCNT (STARTUP_CURRENT_LIMITATION) );
3235 04fb 3530526c mov 21100,#48
3236 ; 1634 TIM1->DTR = (u8)(hCntDeadDtime);
3238 04ff 550030526e mov 21102,_hCntDeadDtime+1
3239 ; 1637 TIM1->OISR = 0; // Default inactive
3241 0504 725f526f clr 21103
3242 ; 1660 TIM1->CCER1 = (A_OFF|B_OFF);
3244 0508 725f525c clr 21084
3245 ; 1662 TIM1->CCER2 = C_OFF;
3247 050c 3510525d mov 21085,#16
3248 ; 1671 TIM1->BKR = (DEV_BKIN_POLARITY|DEV_BKIN|TIM1_OSSISTATE_ENABLE|TIM1_LOCKLEVEL_2);
3250 0510 3506526d mov 21101,#6
3251 ; 1675 TIM1->CR1 |= BIT0;
3253 0514 72105250 bset 21072,#0
3254 ; 1678 TIM1->EGR = (BIT5|BIT0);
3256 0518 35215257 mov 21079,#33
3257 ; 1681 TIM1->IER = BIT7;
3259 051c 35805254 mov 21076,#128
3260 ; 1685 GPIO_Init(ETR_PORT, ETR_PIN,GPIO_MODE_IN_FL_NO_IT);
3262 0520 4b00 push #0
3263 0522 4b10 push #16
3264 0524 ae5023 ldw x,#20515
3265 0527 cd0000 call _GPIO_Init
3267 052a 85 popw x
3268 ; 1687 }
3271 052b 81 ret
3294 ; 1689 void Init_TIM2(void)
3294 ; 1690 {
3295 switch .text
3296 052c _Init_TIM2:
3300 ; 1728 TIM2->CR1 = BIT2;
3302 052c 35045300 mov 21248,#4
3303 ; 1731 TIM2->IER = 0;
3305 0530 725f5301 clr 21249
3306 ; 1733 TIM2->CCER1 = 0;
3308 0534 725f5308 clr 21256
3309 ; 1734 TIM2->CCER2 = 0;
3311 0538 725f5309 clr 21257
3312 ; 1737 TIM2->CCMR1 = BIT0;
3314 053c 35015305 mov 21253,#1
3315 ; 1738 TIM2->CCMR2 = BIT0;
3317 0540 35015306 mov 21254,#1
3318 ; 1739 TIM2->CCMR3 = BIT0;
3320 0544 35015307 mov 21255,#1
3321 ; 1743 TIM2->CCMR1 |= IC_FILTER;
3323 0548 c65305 ld a,21253
3324 ; 1744 TIM2->CCMR2 |= IC_FILTER;
3326 054b c65306 ld a,21254
3327 ; 1745 TIM2->CCMR3 |= IC_FILTER;
3329 054e c65307 ld a,21255
3330 ; 1748 TIM2->PSCR = 0;
3332 0551 725f530c clr 21260
3333 ; 1750 ToCMPxH( TIM2->ARRH, 0xFFFF );
3335 0555 35ff530d mov 21261,#255
3336 ; 1751 ToCMPxL( TIM2->ARRL, 0xFFFF );
3338 0559 35ff530e mov 21262,#255
3339 ; 1754 TIM2->CCER1 |= BIT0;
3341 055d 72105308 bset 21256,#0
3342 ; 1755 TIM2->CCER1 |= BIT4;
3344 0561 72185308 bset 21256,#4
3345 ; 1756 TIM2->CCER2 |= BIT0;
3347 0565 72105309 bset 21257,#0
3348 ; 1759 TIM2->CR1 |= BIT0;
3350 0569 72105300 bset 21248,#0
3351 ; 1761 }
3354 056d 81 ret
3393 ; 1764 void TIM2_InitCapturePolarity(void)
3393 ; 1765 {
3394 switch .text
3395 056e _TIM2_InitCapturePolarity:
3397 056e 88 push a
3398 00000001 OFST: set 1
3401 ; 1766 u8 bHStatus = 0;
3403 056f 0f01 clr (OFST+0,sp)
3404 ; 1767 GPIOD->DDR &= (u8)(~(BIT3|BIT4));
3406 0571 c65011 ld a,20497
3407 0574 a4e7 and a,#231
3408 0576 c75011 ld 20497,a
3409 ; 1768 GPIOA->DDR &= (u8)(~(BIT3));
3411 0579 72175002 bres 20482,#3
3412 ; 1771 if (H1_PORT & H1_PIN)
3414 057d 720750100c btjf 20496,#3,L5121
3415 ; 1773 TIM2->CCER1 |= BIT5;
3417 0582 721a5308 bset 21256,#5
3418 ; 1774 bHStatus |= BIT2;
3420 0586 7b01 ld a,(OFST+0,sp)
3421 0588 aa04 or a,#4
3422 058a 6b01 ld (OFST+0,sp),a
3424 058c 2004 jra L7121
3425 058e L5121:
3426 ; 1778 TIM2->CCER1 &= (u8)(~(BIT5));
3428 058e 721b5308 bres 21256,#5
3429 0592 L7121:
3430 ; 1782 if (H2_PORT & H2_PIN)
3432 0592 720950100c btjf 20496,#4,L1221
3433 ; 1784 TIM2->CCER1 |= BIT1;
3435 0597 72125308 bset 21256,#1
3436 ; 1785 bHStatus |= BIT1;
3438 059b 7b01 ld a,(OFST+0,sp)
3439 059d aa02 or a,#2
3440 059f 6b01 ld (OFST+0,sp),a
3442 05a1 2004 jra L3221
3443 05a3 L1221:
3444 ; 1789 TIM2->CCER1 &= (u8)(~(BIT1));
3446 05a3 72135308 bres 21256,#1
3447 05a7 L3221:
3448 ; 1793 if (H3_PORT & H3_PIN)
3450 05a7 720550100c btjf 20496,#2,L5221
3451 ; 1795 TIM2->CCER2 |= BIT1;
3453 05ac 72125309 bset 21257,#1
3454 ; 1796 bHStatus |= BIT0;
3456 05b0 7b01 ld a,(OFST+0,sp)
3457 05b2 aa01 or a,#1
3458 05b4 6b01 ld (OFST+0,sp),a
3460 05b6 2006 jra L7221
3461 05b8 L5221:
3462 ; 1800 TIM2->CCER2 &= (u8)(~(BIT1));
3464 05b8 72135309 bres 21257,#1
3465 05bc 7b01 ld a,(OFST+0,sp)
3466 05be L7221:
3467 ; 1803 bHallStartStep = bHallSteps[bHStatus];
3469 05be 5f clrw x
3470 05bf 97 ld xl,a
3471 05c0 92d617 ld a,([_bHallSteps.w],x)
3472 05c3 b70c ld _bHallStartStep,a
3473 ; 1805 if (bHallStartStep == NOT_VALID)
3475 05c5 a106 cp a,#6
3476 05c7 2604 jrne L1321
3477 ; 1807 MTC_Status |= MTC_STARTUP_FAILED;
3479 05c9 7212002b bset _MTC_Status,#1
3480 05cd L1321:
3481 ; 1810 TIM2_ClearITPendingBit(TIM2_IT_CC1);
3483 05cd a602 ld a,#2
3484 05cf cd0000 call _TIM2_ClearITPendingBit
3486 ; 1811 TIM2_ClearITPendingBit(TIM2_IT_CC2);
3488 05d2 a604 ld a,#4
3489 05d4 cd0000 call _TIM2_ClearITPendingBit
3491 ; 1⌨️ 快捷键说明
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