📄 mc_stm8s_bldc_drive.ls
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2280 02e3 e711 ld (17,x),a
2281 ; 1069 g_pDevice->regs.r16[VDEV_REG16_HW_ERROR_ACTUAL] |= HEATSINK_TEMPERATURE;
2283 02e5 be01 ldw x,_g_pDevice
2284 02e7 ee02 ldw x,(2,x)
2285 02e9 e613 ld a,(19,x)
2286 02eb aa08 or a,#8
2287 02ed e713 ld (19,x),a
2288 02ef 1e02 ldw x,(OFST-1,sp)
2289 02f1 L517:
2290 ; 1071 if (data < NTC_HYSTERIS)
2292 02f1 a300d1 cpw x,#209
2293 02f4 240e jruge L717
2294 ; 1073 g_pDevice->regs.r16[VDEV_REG16_HW_ERROR_ACTUAL] &= (u8)(~HEATSINK_TEMPERATURE);
2296 02f6 be01 ldw x,_g_pDevice
2297 02f8 ee02 ldw x,(2,x)
2298 02fa e613 ld a,(19,x)
2299 02fc a4f7 and a,#247
2300 02fe e713 ld (19,x),a
2301 0300 6f12 clr (18,x)
2302 0302 1e02 ldw x,(OFST-1,sp)
2303 0304 L717:
2304 ; 1076 temp = (u8)(TEMP_SENS_T0 + (((s16)data - TEMP_SENS_BETA)/TEMP_SENS_ALPHA));
2306 0304 1d003b subw x,#59
2307 0307 a605 ld a,#5
2308 0309 cd0000 call c_sdivx
2310 030c 1c0019 addw x,#25
2311 030f 9f ld a,xl
2312 0310 6b01 ld (OFST-2,sp),a
2313 ; 1077 BLDC_Set_Heatsink_Temperature((u8)(temp));
2315 0312 cd0000 call _BLDC_Set_Heatsink_Temperature
2317 ; 1078 }
2320 0315 5b03 addw sp,#3
2321 0317 81 ret
2359 ; 1088 void GetNeutralPoint(void)
2359 ; 1089 {
2360 switch .text
2361 0318 _GetNeutralPoint:
2363 00000002 OFST: set 2
2366 ; 1091 disableInterrupts();
2369 0318 9b sim
2371 ; 1092 data = ADC_Buffer[ ADC_NEUTRAL_POINT_INDEX ];
2374 0319 be3d ldw x,_ADC_Buffer+8
2375 ; 1093 enableInterrupts();
2378 031b 9a rim
2380 ; 1095 hNeutralPoint = data;
2383 031c bf33 ldw _hNeutralPoint,x
2384 ; 1096 }
2387 031e 81 ret
2426 switch .const
2427 0154 L451:
2428 0154 000003ff dc.l 1023
2429 ; 1098 void GetAsyncUserAdc(void)
2429 ; 1099 {
2430 switch .text
2431 031f _GetAsyncUserAdc:
2433 031f 89 pushw x
2434 00000002 OFST: set 2
2437 ; 1102 disableInterrupts();
2440 0320 9b sim
2442 ; 1103 hAsyncUserAdc = ADC_Buffer[ADC_USER_ASYNC_INDEX];
2445 0321 be3f ldw x,_ADC_Buffer+10
2446 0323 1f01 ldw (OFST-1,sp),x
2447 ; 1104 enableInterrupts();
2450 0325 9a rim
2452 ; 1109 BLDC_Set_Target_rotor_speed((u16)(((u32)MAX_SPEED_RPM * hAsyncUserAdc)/1023));
2455 0326 90ae0546 ldw y,#1350
2456 032a cd0000 call c_umul
2458 032d ae0154 ldw x,#L451
2459 0330 cd0000 call c_ludv
2461 0333 be02 ldw x,c_lreg+2
2462 0335 cd0000 call _BLDC_Set_Target_rotor_speed
2464 ; 1110 if (BLDC_Get_Target_rotor_speed() < MIN_SPEED_01HZ)
2466 0338 cd0000 call _BLDC_Get_Target_rotor_speed
2468 033b a300c8 cpw x,#200
2469 033e 2e06 jrsge L557
2470 ; 1111 BLDC_Set_Target_rotor_speed(MIN_SPEED_01HZ);
2472 0340 ae00c8 ldw x,#200
2473 0343 cd0000 call _BLDC_Set_Target_rotor_speed
2475 0346 L557:
2476 ; 1115 }
2479 0346 85 popw x
2480 0347 81 ret
2525 ; 1117 void Init_ADC( void )
2525 ; 1118 {
2526 switch .text
2527 0348 _Init_ADC:
2529 0348 5203 subw sp,#3
2530 00000003 OFST: set 3
2533 ; 1122 ADC_Sync_State = ADC_USER_SYNC_INIT;
2535 034a 35040007 mov _ADC_Sync_State,#4
2536 ; 1123 ADC_State = ADC_SYNC;
2538 034e 3f41 clr _ADC_State
2539 ; 1125 ADC2->CSR = 0;
2541 0350 725f5400 clr 21504
2542 ; 1129 ADC2->CR1 = BIT5;
2544 0354 35205401 mov 21505,#32
2545 ; 1132 ADC2->CR2 = 0;
2547 0358 725f5402 clr 21506
2548 ; 1135 ADC2->CSR = PHASE_C_BEMF_ADC_CHAN;
2550 035c 35025400 mov 21504,#2
2551 ; 1137 ADC_TDR_tmp = 0;
2553 0360 5f clrw x
2554 0361 1f02 ldw (OFST-1,sp),x
2555 ; 1138 ADC_TDR_tmp |= (u16)(1) << PHASE_A_BEMF_ADC_CHAN;
2557 0363 7b03 ld a,(OFST+0,sp)
2558 ; 1139 ADC_TDR_tmp |= (u16)(1) << PHASE_B_BEMF_ADC_CHAN;
2560 ; 1140 ADC_TDR_tmp |= (u16)(1) << PHASE_C_BEMF_ADC_CHAN;
2562 ; 1142 ADC_TDR_tmp |= (u16)(1) << ADC_CURRENT_CHANNEL;
2564 ; 1143 ADC_TDR_tmp |= (u16)(1) << ADC_USER_SYNC_CHANNEL;
2566 ; 1145 ADC_TDR_tmp |= (u16)(1) << ADC_BUS_CHANNEL;
2568 ; 1146 ADC_TDR_tmp |= (u16)(1) << ADC_NEUTRAL_POINT_CHANNEL;
2570 ; 1147 ADC_TDR_tmp |= (u16)(1) << ADC_TEMP_CHANNEL;
2572 ; 1148 ADC_TDR_tmp |= (u16)(1) << ADC_USER_ASYNC_CHANNEL;
2574 0365 aa17 or a,#23
2575 0367 6b03 ld (OFST+0,sp),a
2576 ; 1150 ToCMPxH( ADC2->TDRH, ADC_TDR_tmp);
2578 0369 725f5406 clr 21510
2579 ; 1151 ToCMPxL( ADC2->TDRL, ADC_TDR_tmp);
2581 036d 35175407 mov 21511,#23
2582 ; 1154 ADC2->CR2 |= BIT6;
2584 0371 721c5402 bset 21506,#6
2585 ; 1157 ADC2->CR1 |= BIT0;
2587 ; 1159 value=30;
2589 0375 a61e ld a,#30
2590 0377 72105401 bset 21505,#0
2591 037b 6b01 ld (OFST-2,sp),a
2593 037d L5001:
2594 ; 1160 while(value--);
2596 037d 7b01 ld a,(OFST-2,sp)
2597 037f 0a01 dec (OFST-2,sp)
2598 0381 4d tnz a
2599 0382 26f9 jrne L5001
2600 ; 1161 ADC2->CR1 |= BIT0; /////////////////
2602 0384 72105401 bset 21505,#0
2603 ; 1163 ADC2->CSR &= (u8)(~BIT7);
2605 0388 721f5400 bres 21504,#7
2606 ; 1164 ADC2->CSR |= BIT5;
2608 ; 1166 }
2611 038c 5b03 addw sp,#3
2612 038e 721a5400 bset 21504,#5
2613 0392 81 ret
2638 ; 1169 void Enable_ADC_BEMF_Sampling( void )
2638 ; 1170 {
2639 switch .text
2640 0393 _Enable_ADC_BEMF_Sampling:
2644 ; 1172 ADC_Sync_State = ADC_BEMF_INIT;
2646 0393 3f07 clr _ADC_Sync_State
2647 ; 1173 }
2650 0395 81 ret
2675 ; 1175 void Enable_ADC_Current_Sampling( void )
2675 ; 1176 {
2676 switch .text
2677 0396 _Enable_ADC_Current_Sampling:
2681 ; 1178 ADC_Sync_State = ADC_CURRENT_INIT;
2683 0396 35120007 mov _ADC_Sync_State,#18
2684 ; 1179 }
2687 039a 81 ret
2712 ; 1181 void Enable_ADC_User_Sync_Sampling( void )
2712 ; 1182 {
2713 switch .text
2714 039b _Enable_ADC_User_Sync_Sampling:
2718 ; 1184 ADC_Sync_State = ADC_USER_SYNC_INIT;
2720 039b 35040007 mov _ADC_Sync_State,#4
2721 ; 1185 }
2724 039f 81 ret
2761 ; 1189 void GetStepTime(void)
2761 ; 1190 {
2762 switch .text
2763 03a0 _GetStepTime:
2765 03a0 89 pushw x
2766 00000002 OFST: set 2
2769 ; 1193 cur_time = hTim3Cnt;
2771 03a1 be1a ldw x,_hTim3Cnt
2772 03a3 1f01 ldw (OFST-1,sp),x
2773 ; 1195 hTim3Cnt = 0;
2775 03a5 5f clrw x
2776 03a6 bf1a ldw _hTim3Cnt,x
2777 ; 1197 Zero_Cross_Time = cur_time;
2779 03a8 1e01 ldw x,(OFST-1,sp)
2780 03aa bf24 ldw _Zero_Cross_Time,x
2781 ; 1198 Zero_Cross_Count++;
2783 ; 1199 }
2786 03ac 85 popw x
2787 03ad 3c1a inc _Zero_Cross_Count
2788 03af 81 ret
2816 ; 1202 void SpeedMeasurement(void)
2816 ; 1203 {
2817 switch .text
2818 03b0 _SpeedMeasurement:
2822 ; 1204 if (first_cap == 0)
2824 03b0 b616 ld a,_first_cap
2825 03b2 2606 jrne L7601
2826 ; 1206 first_cap = 1;
2828 03b4 35010016 mov _first_cap,#1
2829 ; 1207 cap_val = 0;
2830 ; 1208 cap_index = 0;
2832 03b8 2013 jp LC001
2833 03ba L7601:
2834 ; 1212 cap_val += Zero_Cross_Time;
2836 03ba be13 ldw x,_cap_val
2837 03bc 72bb0024 addw x,_Zero_Cross_Time
2838 03c0 bf13 ldw _cap_val,x
2839 ; 1213 cap_index++;
2841 03c2 3c15 inc _cap_index
2842 ; 1215 if (cap_index == CAP_STEP_NUM)
2844 03c4 b615 ld a,_cap_index
2845 03c6 a106 cp a,#6
2846 03c8 2608 jrne L1701
2847 ; 1217 *pcounter_reg = cap_val;
2849 03ca 92cf0a ldw [L51_pcounter_reg.w],x
2850 ; 1218 cap_val = 0;
2852 ; 1219 cap_index = 0;
2854 03cd LC001:
2856 03cd 5f clrw x
2857 03ce bf13 ldw _cap_val,x
2859 03d0 3f15 clr _cap_index
2860 03d2 L1701:
2861 ; 1222 }
2864 03d2 81 ret
2901 ; 1470 @near @interrupt @svlreg void ADC2_IRQHandler (void)
2901 ; 1471 {
2902 switch .text
2903 03d3 _ADC2_IRQHandler:
2905 03d3 8a push cc
2906 03d4 84 pop a
2907 03d5 a4bf and a,#191
2908 03d7 88 push a
2909 03d8 86 pop cc
2910 00000002 OFST: set 2
2911 03d9 3b0002 push c_x+2
2912 03dc be00 ldw x,c_x
2913 03de 89 pushw x
2914 03df 3b0002 push c_y+2
2915 03e2 be00 ldw x,c_y
2916 03e4 89 pushw x
2917 03e5 be02 ldw x,c_lreg+2
2918 03e7 89 pushw x
2919 03e8 be00 ldw x,c_lreg
2920 03ea 89 pushw x
2921 03eb 89 pushw x
2924 ; 1474 data = ADC2->DRH;
2926 03ec c65404 ld a,21508
2927 03ef 5f clrw x
2928 03f0 97 ld xl,a
2929 03f1 1f01 ldw (OFST-1,sp),x
2930 ; 1475 data <<= 2;
2932 03f3 0802 sll (OFST+0,sp)
2933 03f5 0901 rlc (OFST-1,sp)
2934 03f7 0802 sll (OFST+0,sp)
2935 03f9 0901 rlc (OFST-1,sp)
2936 ; 1476 data |= (ADC2->DRL & 0x03);
2938 03fb c65405 ld a,21509
2939 03fe a403 and a,#3
2940 0400 5f clrw x
2941 0401 97 ld xl,a
2942 0402 01 rrwa x,a
2943 0403 1a02 or a,(OFST+0,sp)
2944 0405 01 rrwa x,a
2945 0406 1a01 or a,(OFST-1,sp)
2946 0408 01 rrwa x,a
2947 0409 1f01 ldw (OFST-1,sp),x
2948 ; 1479 ADC2->CSR &= (u8)(~BIT7);
2950 040b 721f5400 bres 21504,#7
2951 ; 1482 switch (ADC_Async_State)
2953 040f b608 ld a,_ADC_Async_State
2955 ; 1510 break;
2956 0411 4a dec a
2957 0412 2712 jreq L7701
2958 0414 a002 sub a,#2
2959 0416 2714 jreq L1011
2960 0418 a002 sub a,#2
2961 041a 2716 jreq L3011
2962 041c a002 sub a,#2
2963 041e 2718 jreq L5011
2964 ; 1484 default:
2964 ; 1485
2964 ; 1486 case ADC_CURRENT_SAMPLE:
2964 ; 1487 ADC_Buffer[ ADC_CURRENT_INDEX ] = data;
2966 0420 bf35 ldw _ADC_Buffer,x
2967 ; 1488 ADC_Async_State = ADC_BUS_INIT;
2969 0422 3f08 clr _ADC_Async_State
2970 ; 1489 break;
2972 0424 2018 jra L1411
2973 0426 L7701:
2974 ; 1492 case ADC_BUS_SAMPLE:
2974 ; 1493 ADC_Buffer[ ADC_BUS_INDEX ] = data;
2976 0426 bf39 ldw _ADC_Buffer+4,x
2977 ; 1494 ADC_Async_State = ADC_TEMP_INIT;
2979 0428 a602 ld a,#2
2980 ; 1495 break;
2982 042a 2010 jp LC002
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