📄 stm8s_spi.ls
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1003 switch .text
1004 00a8 _SPI_GetCRC:
1006 00a8 88 push a
1007 00000001 OFST: set 1
1010 ; 328 u8 crcreg = 0;
1012 ; 331 assert_param(IS_SPI_CRC_OK(SPI_CRC));
1014 ; 333 if (SPI_CRC != SPI_CRC_RX)
1016 00a9 4d tnz a
1017 00aa 2705 jreq L154
1018 ; 335 crcreg = SPI->TXCRCR; /* Get the Tx CRC register*/
1020 00ac c65207 ld a,20999
1022 00af 2003 jra L354
1023 00b1 L154:
1024 ; 339 crcreg = SPI->RXCRCR; /* Get the Rx CRC register*/
1026 00b1 c65206 ld a,20998
1027 00b4 L354:
1028 ; 343 return crcreg;
1032 00b4 5b01 addw sp,#1
1033 00b6 81 ret
1058 ; 359 void SPI_ResetCRC(void)
1058 ; 360 {
1059 switch .text
1060 00b7 _SPI_ResetCRC:
1064 ; 363 SPI_CalculateCRCCmd(ENABLE);
1066 00b7 a601 ld a,#1
1067 00b9 add9 call _SPI_CalculateCRCCmd
1069 ; 366 SPI_Cmd(ENABLE);
1071 00bb a601 ld a,#1
1073 ; 367 }
1076 00bd 2087 jp _SPI_Cmd
1100 ; 384 u8 SPI_GetCRCPolynomial(void)
1100 ; 385 {
1101 switch .text
1102 00bf _SPI_GetCRCPolynomial:
1106 ; 386 return SPI->CRCPR; /* Return the CRC polynomial register */
1108 00bf c65205 ld a,20997
1111 00c2 81 ret
1167 ; 402 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)
1167 ; 403 {
1168 switch .text
1169 00c3 _SPI_BiDirectionalLineConfig:
1173 ; 405 assert_param(IS_SPI_DIRECTION_OK(SPI_Direction));
1175 ; 407 if (SPI_Direction != SPI_DIRECTION_RX)
1177 00c3 4d tnz a
1178 00c4 2705 jreq L325
1179 ; 409 SPI->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
1181 00c6 721c5201 bset 20993,#6
1184 00ca 81 ret
1185 00cb L325:
1186 ; 413 SPI->CR2 &= (u8)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
1188 00cb 721d5201 bres 20993,#6
1189 ; 415 }
1192 00cf 81 ret
1313 ; 435 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)
1313 ; 436 {
1314 switch .text
1315 00d0 _SPI_GetFlagStatus:
1317 00d0 88 push a
1318 00000001 OFST: set 1
1321 ; 437 FlagStatus status = RESET;
1323 ; 439 assert_param(IS_SPI_FLAGS_OK(SPI_FLAG));
1325 ; 442 if ((SPI->SR & (u8)SPI_FLAG) != (u8)RESET)
1327 00d1 c45203 and a,20995
1328 00d4 2702 jreq L306
1329 ; 444 status = SET; /* SPI_FLAG is set */
1331 00d6 a601 ld a,#1
1333 00d8 L306:
1334 ; 448 status = RESET; /* SPI_FLAG is reset*/
1336 ; 452 return status;
1340 00d8 5b01 addw sp,#1
1341 00da 81 ret
1376 ; 479 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)
1376 ; 480 {
1377 switch .text
1378 00db _SPI_ClearFlag:
1382 ; 481 assert_param(IS_SPI_CLEAR_FLAGS_OK(SPI_FLAG));
1384 ; 483 SPI->SR = (u8)(~SPI_FLAG);
1386 00db 43 cpl a
1387 00dc c75203 ld 20995,a
1388 ; 484 }
1391 00df 81 ret
1473 ; 509 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)
1473 ; 510 {
1474 switch .text
1475 00e0 _SPI_GetITStatus:
1477 00e0 88 push a
1478 00e1 89 pushw x
1479 00000002 OFST: set 2
1482 ; 511 ITStatus pendingbitstatus = RESET;
1484 ; 512 u8 itpos = 0;
1486 ; 513 u8 itmask1 = 0;
1488 ; 514 u8 itmask2 = 0;
1490 ; 515 u8 enablestatus = 0;
1492 ; 516 assert_param(IS_SPI_GET_IT_OK(SPI_IT));
1494 ; 518 itpos = (u8)((u8)1 << ((u8)SPI_IT & (u8)0x0F));
1496 00e2 a40f and a,#15
1497 00e4 5f clrw x
1498 00e5 97 ld xl,a
1499 00e6 a601 ld a,#1
1500 00e8 5d tnzw x
1501 00e9 2704 jreq L65
1502 00eb L06:
1503 00eb 48 sll a
1504 00ec 5a decw x
1505 00ed 26fc jrne L06
1506 00ef L65:
1507 00ef 6b01 ld (OFST-1,sp),a
1508 ; 521 itmask1 = (u8)((u8)SPI_IT >> (u8)4);
1510 00f1 7b03 ld a,(OFST+1,sp)
1511 00f3 4e swap a
1512 00f4 a40f and a,#15
1513 00f6 6b02 ld (OFST+0,sp),a
1514 ; 523 itmask2 = (u8)((u8)1 << itmask1);
1516 00f8 5f clrw x
1517 00f9 97 ld xl,a
1518 00fa a601 ld a,#1
1519 00fc 5d tnzw x
1520 00fd 2704 jreq L26
1521 00ff L46:
1522 00ff 48 sll a
1523 0100 5a decw x
1524 0101 26fc jrne L46
1525 0103 L26:
1526 ; 525 enablestatus = (u8)((u8)SPI->ICR & itmask2);
1528 0103 c45202 and a,20994
1529 0106 6b02 ld (OFST+0,sp),a
1530 ; 527 if (((SPI->SR & itpos) != RESET) && enablestatus)
1532 0108 c65203 ld a,20995
1533 010b 1501 bcp a,(OFST-1,sp)
1534 010d 2708 jreq L766
1536 010f 7b02 ld a,(OFST+0,sp)
1537 0111 2704 jreq L766
1538 ; 530 pendingbitstatus = SET;
1540 0113 a601 ld a,#1
1542 0115 2001 jra L176
1543 0117 L766:
1544 ; 535 pendingbitstatus = RESET;
1546 0117 4f clr a
1547 0118 L176:
1548 ; 538 return pendingbitstatus;
1552 0118 5b03 addw sp,#3
1553 011a 81 ret
1598 ; 564 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)
1598 ; 565 {
1599 switch .text
1600 011b _SPI_ClearITPendingBit:
1602 011b 88 push a
1603 00000001 OFST: set 1
1606 ; 566 u8 itpos = 0;
1608 ; 567 assert_param(IS_SPI_CLEAR_IT_OK(SPI_IT));
1610 ; 572 itpos = (u8)((u8)1 << (((u8)SPI_IT & (u8)0xF0) >> 4));
1612 011c 4e swap a
1613 011d a40f and a,#15
1614 011f 5f clrw x
1615 0120 97 ld xl,a
1616 0121 a601 ld a,#1
1617 0123 5d tnzw x
1618 0124 2704 jreq L07
1619 0126 L27:
1620 0126 48 sll a
1621 0127 5a decw x
1622 0128 26fc jrne L27
1623 012a L07:
1624 ; 574 SPI->SR = (u8)(~itpos);
1626 012a 43 cpl a
1627 012b c75203 ld 20995,a
1628 ; 576 }
1631 012e 84 pop a
1632 012f 81 ret
1645 xdef _SPI_ClearITPendingBit
1646 xdef _SPI_GetITStatus
1647 xdef _SPI_ClearFlag
1648 xdef _SPI_GetFlagStatus
1649 xdef _SPI_BiDirectionalLineConfig
1650 xdef _SPI_GetCRCPolynomial
1651 xdef _SPI_ResetCRC
1652 xdef _SPI_GetCRC
1653 xdef _SPI_CalculateCRCCmd
1654 xdef _SPI_TransmitCRC
1655 xdef _SPI_NSSInternalSoftwareCmd
1656 xdef _SPI_ReceiveData
1657 xdef _SPI_SendData
1658 xdef _SPI_ITConfig
1659 xdef _SPI_Cmd
1660 xdef _SPI_Init
1661 xdef _SPI_DeInit
1680 end
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