📄 stm8s_uart3.ls
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813 016b 2035 jp LC001
814 016d L772:
815 ; 255 if (uartreg == 0x01)
817 016d 7b01 ld a,(OFST-1,sp)
818 016f a101 cp a,#1
819 0171 260b jrne L713
820 ; 257 UART3->CR1 &= (u8)(~itpos);
822 0173 7b02 ld a,(OFST+0,sp)
823 0175 43 cpl a
824 0176 c45244 and a,21060
825 0179 LC003:
826 0179 c75244 ld 21060,a
828 017c 2027 jra L513
829 017e L713:
830 ; 259 else if (uartreg == 0x02)
832 017e a102 cp a,#2
833 0180 260b jrne L323
834 ; 261 UART3->CR2 &= (u8)(~itpos);
836 0182 7b02 ld a,(OFST+0,sp)
837 0184 43 cpl a
838 0185 c45245 and a,21061
839 0188 LC002:
840 0188 c75245 ld 21061,a
842 018b 2018 jra L513
843 018d L323:
844 ; 263 else if (uartreg == 0x03)
846 018d a103 cp a,#3
847 018f 260b jrne L723
848 ; 265 UART3->CR4 &= (u8)(~itpos);
850 0191 7b02 ld a,(OFST+0,sp)
851 0193 43 cpl a
852 0194 c45247 and a,21063
853 0197 LC004:
854 0197 c75247 ld 21063,a
856 019a 2009 jra L513
857 019c L723:
858 ; 269 UART3->CR6 &= (u8)(~itpos);
860 019c 7b02 ld a,(OFST+0,sp)
861 019e 43 cpl a
862 019f c45249 and a,21065
863 01a2 LC001:
864 01a2 c75249 ld 21065,a
865 01a5 L513:
866 ; 272 }
869 01a5 5b04 addw sp,#4
870 01a7 81 ret
929 ; 290 void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
929 ; 291 {
930 switch .text
931 01a8 _UART3_LINBreakDetectionConfig:
935 ; 292 assert_param(IS_UART3_LINBREAKDETECTIONLENGTH_OK(UART3_LINBreakDetectionLength));
937 ; 294 if (UART3_LINBreakDetectionLength != UART3_LINBREAKDETECTIONLENGTH_10BITS)
939 01a8 4d tnz a
940 01a9 2705 jreq L163
941 ; 296 UART3->CR4 |= UART3_CR4_LBDL;
943 01ab 721a5247 bset 21063,#5
946 01af 81 ret
947 01b0 L163:
948 ; 300 UART3->CR4 &= ((u8)~UART3_CR4_LBDL);
950 01b0 721b5247 bres 21063,#5
951 ; 302 }
954 01b4 81 ret
1075 ; 324 void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
1075 ; 325 {
1076 switch .text
1077 01b5 _UART3_LINConfig:
1079 01b5 89 pushw x
1080 00000000 OFST: set 0
1083 ; 326 assert_param(IS_UART3_SLAVE_OK(UART3_Mode));
1085 ; 328 assert_param(IS_UART3_AUTOSYNC_OK(UART3_Autosync));
1087 ; 330 assert_param(IS_UART3_DIVUP_OK(UART3_DivUp));
1089 ; 332 if (UART3_Mode != UART3_LIN_MODE_MASTER)
1091 01b6 9e ld a,xh
1092 01b7 4d tnz a
1093 01b8 2706 jreq L344
1094 ; 334 UART3->CR6 |= UART3_CR6_LSLV;
1096 01ba 721a5249 bset 21065,#5
1098 01be 2004 jra L544
1099 01c0 L344:
1100 ; 338 UART3->CR6 &= ((u8)~UART3_CR6_LSLV);
1102 01c0 721b5249 bres 21065,#5
1103 01c4 L544:
1104 ; 341 if (UART3_Autosync != UART3_LIN_AUTOSYNC_DISABLE)
1106 01c4 7b02 ld a,(OFST+2,sp)
1107 01c6 2706 jreq L744
1108 ; 343 UART3->CR6 |= UART3_CR6_LASE ;
1110 01c8 72185249 bset 21065,#4
1112 01cc 2004 jra L154
1113 01ce L744:
1114 ; 347 UART3->CR6 &= ((u8)~ UART3_CR6_LASE );
1116 01ce 72195249 bres 21065,#4
1117 01d2 L154:
1118 ; 350 if (UART3_DivUp != UART3_LIN_DIVUP_LBRR1)
1120 01d2 7b05 ld a,(OFST+5,sp)
1121 01d4 2706 jreq L354
1122 ; 352 UART3->CR6 |= UART3_CR6_LDUM;
1124 01d6 721e5249 bset 21065,#7
1126 01da 2004 jra L554
1127 01dc L354:
1128 ; 356 UART3->CR6 &= ((u8)~ UART3_CR6_LDUM);
1130 01dc 721f5249 bres 21065,#7
1131 01e0 L554:
1132 ; 359 }
1135 01e0 85 popw x
1136 01e1 81 ret
1171 ; 379 void UART3_LINCmd(FunctionalState NewState)
1171 ; 380 {
1172 switch .text
1173 01e2 _UART3_LINCmd:
1177 ; 381 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1179 ; 383 if (NewState != DISABLE)
1181 01e2 4d tnz a
1182 01e3 2705 jreq L574
1183 ; 386 UART3->CR3 |= UART3_CR3_LINEN;
1185 01e5 721c5246 bset 21062,#6
1188 01e9 81 ret
1189 01ea L574:
1190 ; 391 UART3->CR3 &= ((u8)~UART3_CR3_LINEN);
1192 01ea 721d5246 bres 21062,#6
1193 ; 393 }
1196 01ee 81 ret
1253 ; 412 void UART3_WakeUpConfig(UART3_WakeUp_TypeDef UART3_WakeUp)
1253 ; 413 {
1254 switch .text
1255 01ef _UART3_WakeUpConfig:
1259 ; 414 assert_param(IS_UART3_WAKEUP_OK(UART3_WakeUp));
1261 ; 416 UART3->CR1 &= ((u8)~UART3_CR1_WAKE);
1263 01ef 72175244 bres 21060,#3
1264 ; 417 UART3->CR1 |= (u8)UART3_WakeUp;
1266 01f3 ca5244 or a,21060
1267 01f6 c75244 ld 21060,a
1268 ; 418 }
1271 01f9 81 ret
1307 ; 438 void UART3_ReceiverWakeUpCmd(FunctionalState NewState)
1307 ; 439 {
1308 switch .text
1309 01fa _UART3_ReceiverWakeUpCmd:
1313 ; 440 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1315 ; 442 if (NewState != DISABLE)
1317 01fa 4d tnz a
1318 01fb 2705 jreq L545
1319 ; 445 UART3->CR2 |= UART3_CR2_RWU;
1321 01fd 72125245 bset 21061,#1
1324 0201 81 ret
1325 0202 L545:
1326 ; 450 UART3->CR2 &= ((u8)~UART3_CR2_RWU);
1328 0202 72135245 bres 21061,#1
1329 ; 452 }
1332 0206 81 ret
1355 ; 470 u8 UART3_ReceiveData8(void)
1355 ; 471 {
1356 switch .text
1357 0207 _UART3_ReceiveData8:
1361 ; 472 return ((u8)UART3->DR);
1363 0207 c65241 ld a,21057
1366 020a 81 ret
1389 ; 490 u16 UART3_ReceiveData9(void)
1389 ; 491 {
1390 switch .text
1391 020b _UART3_ReceiveData9:
1393 020b 89 pushw x
1394 00000002 OFST: set 2
1397 ; 492 return (u16)((((u16)UART3->DR) | ((u16)(((u16)((u16)UART3->CR1 & (u16)UART3_CR1_R8)) << 1))) & ((u16)0x01FF));
1399 020c c65244 ld a,21060
1400 020f a480 and a,#128
1401 0211 5f clrw x
1402 0212 02 rlwa x,a
1403 0213 58 sllw x
1404 0214 1f01 ldw (OFST-1,sp),x
1405 0216 5f clrw x
1406 0217 c65241 ld a,21057
1407 021a 97 ld xl,a
1408 021b 01 rrwa x,a
1409 021c 1a02 or a,(OFST+0,sp)
1410 021e 01 rrwa x,a
1411 021f 1a01 or a,(OFST-1,sp)
1412 0221 a401 and a,#1
1413 0223 01 rrwa x,a
1416 0224 5b02 addw sp,#2
1417 0226 81 ret
1451 ; 514 void UART3_SendData8(u8 Data)
1451 ; 515 {
1452 switch .text
1453 0227 _UART3_SendData8:
1457 ; 517 UART3->DR = Data;
1459 0227 c75241 ld 21057,a
1460 ; 518 }
1463 022a 81 ret
1497 ; 537 void UART3_SendData9(u16 Data)
1497 ; 538 {
1498 switch .text
1499 022b _UART3_SendData9:
1501 022b 89 pushw x
1502 00000000 OFST: set 0
1505 ; 539 UART3->CR1 &= ((u8)~UART3_CR1_T8); /**< Clear the transmit data bit 8 */
1507 022c 721d5244 bres 21060,#6
1508 ; 540 UART3->CR1 |= (u8)(((u8)(Data >> 2)) & UART3_CR1_T8); /**< Write the transmit data bit [8] */
1510 0230 54 srlw x
1511 0231 54 srlw x
1512 0232 9f ld a,xl
1513 0233 a440 and a,#64
1514 0235 ca5244 or a,21060
1515 0238 c75244 ld 21060,a
1516 ; 541 UART3->DR = (u8)(Data); /**< Write the transmit data bit [0:7] */
1518 023b 7b02 ld a,(OFST+2,sp)
1519 023d c75241 ld 21057,a
1520 ; 543 }
1523 0240 85 popw x
1524 0241 81 ret
1547 ; 558 void UART3_SendBreak(void)
1547 ; 559 {
1548 switch .text
1549 0242 _UART3_SendBreak:
1553 ; 560 UART3->CR2 |= UART3_CR2_SBK;
1555 0242 72105245 bset 21061,#0
1556 ; 561 }
1559 0246 81 ret
1593 ; 580 void UART3_SetAddress(u8 UART3_Address)
1593 ; 581 {
1594 switch .text
1595 0247 _UART3_SetAddress:
1597 0247 88 push a
1598 00000000 OFST: set 0
1601 ; 583 assert_param(IS_UART3_ADDRESS_OK(UART3_Address));
1603 ; 586 UART3->CR4 &= ((u8)~UART3_CR4_ADD);
1605 0248 c65247 ld a,21063
1606 024b a4f0 and a,#240
1607 024d c75247 ld 21063,a
1608 ; 588 UART3->CR4 |= UART3_Address;
1610 0250 c65247 ld a,21063
1611 0253 1a01 or a,(OFST+1,sp)
1612 0255 c75247 ld 21063,a
1613 ; 589 }
1616 0258 84 pop a
1617 0259 81 ret
1774 ; 609 FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG)
1774 ; 610 {
1775 switch .text
1776 025a _UART3_GetFlagStatus:
1778 025a 89 pushw x
1779 025b 88 push a
1780 00000001 OFST: set 1
1783 ; 611 FlagStatus status = RESET;
1785 ; 614 assert_param(IS_UART3_FLAG_OK(UART3_FLAG));
1787 ; 617 if (UART3_FLAG == UART3_FLAG_LBDF)
1789 025c a30210 cpw x,#528
1790 025f 2608 jrne L147
1791 ; 619 if ((UART3->CR4 & (u8)UART3_FLAG) != (u8)0x00)
1793 0261 9f ld a,xl
1794 0262 c45247 and a,21063
1795 0265 2728 jreq L747
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