📄 stm8s_uart3.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
58 ; 66 void UART3_DeInit(void)
58 ; 67 {
60 switch .text
61 0000 _UART3_DeInit:
63 00000001 OFST: set 1
66 ; 68 u8 dummy = 0;
68 ; 71 dummy = UART3->SR;
70 0000 c65240 ld a,21056
71 ; 72 dummy = UART3->DR;
73 0003 c65241 ld a,21057
74 ; 74 UART3->BRR2 = UART3_BRR2_RESET_VALUE; /*< Set UART3_BRR2 to reset value 0x00 */
76 0006 725f5243 clr 21059
77 ; 75 UART3->BRR1 = UART3_BRR1_RESET_VALUE; /*< Set UART3_BRR1 to reset value 0x00 */
79 000a 725f5242 clr 21058
80 ; 77 UART3->CR1 = UART3_CR1_RESET_VALUE; /*< Set UART3_CR1 to reset value 0x00 */
82 000e 725f5244 clr 21060
83 ; 78 UART3->CR2 = UART3_CR2_RESET_VALUE; /*< Set UART3_CR2 to reset value 0x00 */
85 0012 725f5245 clr 21061
86 ; 79 UART3->CR3 = UART3_CR3_RESET_VALUE; /*< Set UART3_CR3 to reset value 0x00 */
88 0016 725f5246 clr 21062
89 ; 80 UART3->CR4 = UART3_CR4_RESET_VALUE; /*< Set UART3_CR4 to reset value 0x00 */
91 001a 725f5247 clr 21063
92 ; 81 UART3->CR6 = UART3_CR6_RESET_VALUE; /*< Set UART3_CR6 to reset value 0x00 */
94 001e 725f5249 clr 21065
95 ; 83 }
98 0022 81 ret
325 .const: section .text
326 0000 L41:
327 0000 00000064 dc.l 100
328 ; 102 void UART3_Init(u32 BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
328 ; 103 {
329 switch .text
330 0023 _UART3_Init:
332 0000000e OFST: set 14
335 ; 104 u8 BRR2_1, BRR2_2 = 0;
337 ; 105 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
339 ; 107 assert_param(IS_UART3_WORDLENGTH_OK(WordLength));
341 ; 109 assert_param(IS_UART3_STOPBITS_OK(StopBits));
343 ; 111 assert_param(IS_UART3_PARITY_OK(Parity));
345 ; 114 assert_param(IS_UART3_BAUDRATE_OK(BaudRate));
347 ; 117 assert_param(IS_UART3_MODE_OK((u8)Mode));
349 ; 122 UART3->CR1 &= (u8)(~UART3_CR1_M); /**< Clear the word length bit */
351 0023 72195244 bres 21060,#4
352 0027 520e subw sp,#14
353 ; 123 UART3->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART3_WordLength value */
355 0029 c65244 ld a,21060
356 002c 1a15 or a,(OFST+7,sp)
357 002e c75244 ld 21060,a
358 ; 125 UART3->CR3 &= (u8)(~UART3_CR3_STOP); /**< Clear the STOP bits */
360 0031 c65246 ld a,21062
361 0034 a4cf and a,#207
362 0036 c75246 ld 21062,a
363 ; 126 UART3->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART3_StopBits value */
365 0039 c65246 ld a,21062
366 003c 1a16 or a,(OFST+8,sp)
367 003e c75246 ld 21062,a
368 ; 128 UART3->CR1 &= (u8)(~(UART3_CR1_PCEN | UART3_CR1_PS)); /**< Clear the Parity Control bit */
370 0041 c65244 ld a,21060
371 0044 a4f9 and a,#249
372 0046 c75244 ld 21060,a
373 ; 129 UART3->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART3_Parity value */
375 0049 c65244 ld a,21060
376 004c 1a17 or a,(OFST+9,sp)
377 004e c75244 ld 21060,a
378 ; 131 UART3->BRR1 &= (u8)(~UART3_BRR1_DIVM); /**< Clear the LSB mantissa of UART3DIV */
380 0051 725f5242 clr 21058
381 ; 132 UART3->BRR2 &= (u8)(~UART3_BRR2_DIVM); /**< Clear the MSB mantissa of UART3DIV */
383 0055 c65243 ld a,21059
384 0058 a40f and a,#15
385 005a c75243 ld 21059,a
386 ; 133 UART3->BRR2 &= (u8)(~UART3_BRR2_DIVF); /**< Clear the Fraction bits of UART3DIV */
388 005d c65243 ld a,21059
389 0060 a4f0 and a,#240
390 0062 c75243 ld 21059,a
391 ; 136 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
393 0065 96 ldw x,sp
394 0066 1c0011 addw x,#OFST+3
395 0069 cd0000 call c_ltor
397 006c a604 ld a,#4
398 006e cd0000 call c_llsh
400 0071 96 ldw x,sp
401 0072 5c incw x
402 0073 cd0000 call c_rtol
404 0076 cd0000 call _CLK_GetClockFreq
406 0079 96 ldw x,sp
407 007a 5c incw x
408 007b cd0000 call c_ludv
410 007e 96 ldw x,sp
411 007f 1c000b addw x,#OFST-3
412 0082 cd0000 call c_rtol
414 ; 137 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
416 0085 96 ldw x,sp
417 0086 1c0011 addw x,#OFST+3
418 0089 cd0000 call c_ltor
420 008c a604 ld a,#4
421 008e cd0000 call c_llsh
423 0091 96 ldw x,sp
424 0092 5c incw x
425 0093 cd0000 call c_rtol
427 0096 cd0000 call _CLK_GetClockFreq
429 0099 a664 ld a,#100
430 009b cd0000 call c_smul
432 009e 96 ldw x,sp
433 009f 5c incw x
434 00a0 cd0000 call c_ludv
436 00a3 96 ldw x,sp
437 00a4 1c0007 addw x,#OFST-7
438 00a7 cd0000 call c_rtol
440 ; 139 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
440 ; 140 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UART3DIV */
442 00aa 96 ldw x,sp
443 00ab 1c000b addw x,#OFST-3
444 00ae cd0000 call c_ltor
446 00b1 a664 ld a,#100
447 00b3 cd0000 call c_smul
449 00b6 96 ldw x,sp
450 00b7 5c incw x
451 00b8 cd0000 call c_rtol
453 00bb 96 ldw x,sp
454 00bc 1c0007 addw x,#OFST-7
455 00bf cd0000 call c_ltor
457 00c2 96 ldw x,sp
458 00c3 5c incw x
459 00c4 cd0000 call c_lsub
461 00c7 a604 ld a,#4
462 00c9 cd0000 call c_llsh
464 00cc ae0000 ldw x,#L41
465 00cf cd0000 call c_ludv
467 00d2 b603 ld a,c_lreg+3
468 00d4 a40f and a,#15
469 00d6 6b05 ld (OFST-9,sp),a
470 ; 141 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
472 00d8 96 ldw x,sp
473 00d9 1c000b addw x,#OFST-3
474 00dc cd0000 call c_ltor
476 00df a604 ld a,#4
477 00e1 cd0000 call c_lursh
479 00e4 b603 ld a,c_lreg+3
480 00e6 a4f0 and a,#240
481 00e8 b703 ld c_lreg+3,a
482 00ea 3f02 clr c_lreg+2
483 00ec 3f01 clr c_lreg+1
484 00ee 3f00 clr c_lreg
485 00f0 6b06 ld (OFST-8,sp),a
486 ; 143 UART3->BRR2 = (u8)(BRR2_1 | BRR2_2);
488 00f2 1a05 or a,(OFST-9,sp)
489 00f4 c75243 ld 21059,a
490 ; 144 UART3->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UART3DIV */
492 00f7 7b0e ld a,(OFST+0,sp)
493 00f9 c75242 ld 21058,a
494 ; 146 if ((u8)Mode&(u8)UART3_MODE_TX_ENABLE)
496 00fc 7b18 ld a,(OFST+10,sp)
497 00fe a504 bcp a,#4
498 0100 2706 jreq L551
499 ; 148 UART3->CR2 |= UART3_CR2_TEN; /**< Set the Transmitter Enable bit */
501 0102 72165245 bset 21061,#3
503 0106 2004 jra L751
504 0108 L551:
505 ; 152 UART3->CR2 &= (u8)(~UART3_CR2_TEN); /**< Clear the Transmitter Disable bit */
507 0108 72175245 bres 21061,#3
508 010c L751:
509 ; 154 if ((u8)Mode & (u8)UART3_MODE_RX_ENABLE)
511 010c a508 bcp a,#8
512 010e 2706 jreq L161
513 ; 156 UART3->CR2 |= UART3_CR2_REN; /**< Set the Receiver Enable bit */
515 0110 72145245 bset 21061,#2
517 0114 2004 jra L361
518 0116 L161:
519 ; 160 UART3->CR2 &= (u8)(~UART3_CR2_REN); /**< Clear the Receiver Disable bit */
521 0116 72155245 bres 21061,#2
522 011a L361:
523 ; 162 }
526 011a 5b0e addw sp,#14
527 011c 81 ret
582 ; 182 void UART3_Cmd(FunctionalState NewState)
582 ; 183 {
583 switch .text
584 011d _UART3_Cmd:
588 ; 185 if (NewState != DISABLE)
590 011d 4d tnz a
591 011e 2705 jreq L312
592 ; 187 UART3->CR1 &= (u8)(~UART3_CR1_UARTD); /**< UART3 Enable */
594 0120 721b5244 bres 21060,#5
597 0124 81 ret
598 0125 L312:
599 ; 191 UART3->CR1 |= UART3_CR1_UARTD; /**< UART3 Disable (for low power consumption) */
601 0125 721a5244 bset 21060,#5
602 ; 193 }
605 0129 81 ret
737 ; 220 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
737 ; 221 {
738 switch .text
739 012a _UART3_ITConfig:
741 012a 89 pushw x
742 012b 89 pushw x
743 00000002 OFST: set 2
746 ; 222 u8 uartreg, itpos = 0x00;
748 ; 223 assert_param(IS_UART3_CONFIG_IT_OK(UART3_IT));
750 ; 224 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
752 ; 227 uartreg = (u8)(UART3_IT >> 0x08);
754 012c 9e ld a,xh
755 012d 6b01 ld (OFST-1,sp),a
756 ; 230 itpos = (u8)((u8)1 << (u8)((u8)UART3_IT & (u8)0x0F));
758 012f 9f ld a,xl
759 0130 a40f and a,#15
760 0132 5f clrw x
761 0133 97 ld xl,a
762 0134 a601 ld a,#1
763 0136 5d tnzw x
764 0137 2704 jreq L22
765 0139 L42:
766 0139 48 sll a
767 013a 5a decw x
768 013b 26fc jrne L42
769 013d L22:
770 013d 6b02 ld (OFST+0,sp),a
771 ; 232 if (NewState != DISABLE)
773 013f 7b07 ld a,(OFST+5,sp)
774 0141 272a jreq L772
775 ; 235 if (uartreg == 0x01)
777 0143 7b01 ld a,(OFST-1,sp)
778 0145 a101 cp a,#1
779 0147 2607 jrne L103
780 ; 237 UART3->CR1 |= itpos;
782 0149 c65244 ld a,21060
783 014c 1a02 or a,(OFST+0,sp)
785 014e 2029 jp LC003
786 0150 L103:
787 ; 239 else if (uartreg == 0x02)
789 0150 a102 cp a,#2
790 0152 2607 jrne L503
791 ; 241 UART3->CR2 |= itpos;
793 0154 c65245 ld a,21061
794 0157 1a02 or a,(OFST+0,sp)
796 0159 202d jp LC002
797 015b L503:
798 ; 243 else if (uartreg == 0x03)
800 015b a103 cp a,#3
801 015d 2607 jrne L113
802 ; 245 UART3->CR4 |= itpos;
804 015f c65247 ld a,21063
805 0162 1a02 or a,(OFST+0,sp)
807 0164 2031 jp LC004
808 0166 L113:
809 ; 249 UART3->CR6 |= itpos;
811 0166 c65249 ld a,21065
812 0169 1a02 or a,(OFST+0,sp)
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