📄 stm8s_tim2.ls
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1163 0159 a602 ld a,#2
1165 015b 2002 jra L564
1166 015d L364:
1167 ; 395 icselection = (u8)TIM2_ICSELECTION_DIRECTTI;
1169 015d a601 ld a,#1
1170 015f L564:
1171 015f 6b02 ld (OFST+0,sp),a
1172 ; 398 if (TIM2_Channel == TIM2_CHANNEL_1)
1174 0161 7b03 ld a,(OFST+1,sp)
1175 0163 2626 jrne L764
1176 ; 401 TI1_Config(TIM2_ICPolarity, TIM2_ICSelection,
1176 ; 402 TIM2_ICFilter);
1178 0165 7b09 ld a,(OFST+7,sp)
1179 0167 88 push a
1180 0168 7b08 ld a,(OFST+6,sp)
1181 016a 97 ld xl,a
1182 016b 7b05 ld a,(OFST+3,sp)
1183 016d 95 ld xh,a
1184 016e cd0410 call L3_TI1_Config
1186 0171 84 pop a
1187 ; 405 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1189 0172 7b08 ld a,(OFST+6,sp)
1190 0174 cd032c call _TIM2_SetIC1Prescaler
1192 ; 408 TI2_Config(icpolarity, icselection, TIM2_ICFilter);
1194 0177 7b09 ld a,(OFST+7,sp)
1195 0179 88 push a
1196 017a 7b03 ld a,(OFST+1,sp)
1197 017c 97 ld xl,a
1198 017d 7b02 ld a,(OFST+0,sp)
1199 017f 95 ld xh,a
1200 0180 cd0440 call L5_TI2_Config
1202 0183 84 pop a
1203 ; 411 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1205 0184 7b08 ld a,(OFST+6,sp)
1206 0186 cd0339 call _TIM2_SetIC2Prescaler
1209 0189 2024 jra L174
1210 018b L764:
1211 ; 416 TI2_Config(TIM2_ICPolarity, TIM2_ICSelection,
1211 ; 417 TIM2_ICFilter);
1213 018b 7b09 ld a,(OFST+7,sp)
1214 018d 88 push a
1215 018e 7b08 ld a,(OFST+6,sp)
1216 0190 97 ld xl,a
1217 0191 7b05 ld a,(OFST+3,sp)
1218 0193 95 ld xh,a
1219 0194 cd0440 call L5_TI2_Config
1221 0197 84 pop a
1222 ; 420 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1224 0198 7b08 ld a,(OFST+6,sp)
1225 019a cd0339 call _TIM2_SetIC2Prescaler
1227 ; 423 TI1_Config(icpolarity, icselection, TIM2_ICFilter);
1229 019d 7b09 ld a,(OFST+7,sp)
1230 019f 88 push a
1231 01a0 7b03 ld a,(OFST+1,sp)
1232 01a2 97 ld xl,a
1233 01a3 7b02 ld a,(OFST+0,sp)
1234 01a5 95 ld xh,a
1235 01a6 cd0410 call L3_TI1_Config
1237 01a9 84 pop a
1238 ; 426 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1240 01aa 7b08 ld a,(OFST+6,sp)
1241 01ac cd032c call _TIM2_SetIC1Prescaler
1243 01af L174:
1244 ; 428 }
1247 01af 5b04 addw sp,#4
1248 01b1 81 ret
1303 ; 446 void TIM2_Cmd(FunctionalState NewState)
1303 ; 447 {
1304 switch .text
1305 01b2 _TIM2_Cmd:
1309 ; 449 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1311 ; 452 if (NewState != DISABLE)
1313 01b2 4d tnz a
1314 01b3 2705 jreq L125
1315 ; 454 TIM2->CR1 |= TIM2_CR1_CEN;
1317 01b5 72105300 bset 21248,#0
1320 01b9 81 ret
1321 01ba L125:
1322 ; 458 TIM2->CR1 &= (u8)(~TIM2_CR1_CEN);
1324 01ba 72115300 bres 21248,#0
1325 ; 460 }
1328 01be 81 ret
1407 ; 485 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
1407 ; 486 {
1408 switch .text
1409 01bf _TIM2_ITConfig:
1411 01bf 89 pushw x
1412 00000000 OFST: set 0
1415 ; 488 assert_param(IS_TIM2_IT_OK(TIM2_IT));
1417 ; 489 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1419 ; 491 if (NewState != DISABLE)
1421 01c0 9f ld a,xl
1422 01c1 4d tnz a
1423 01c2 2706 jreq L365
1424 ; 494 TIM2->IER |= TIM2_IT;
1426 01c4 9e ld a,xh
1427 01c5 ca5301 or a,21249
1429 01c8 2006 jra L565
1430 01ca L365:
1431 ; 499 TIM2->IER &= (u8)(~TIM2_IT);
1433 01ca 7b01 ld a,(OFST+1,sp)
1434 01cc 43 cpl a
1435 01cd c45301 and a,21249
1436 01d0 L565:
1437 01d0 c75301 ld 21249,a
1438 ; 501 }
1441 01d3 85 popw x
1442 01d4 81 ret
1478 ; 519 void TIM2_UpdateDisableConfig(FunctionalState NewState)
1478 ; 520 {
1479 switch .text
1480 01d5 _TIM2_UpdateDisableConfig:
1484 ; 522 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1486 ; 525 if (NewState != DISABLE)
1488 01d5 4d tnz a
1489 01d6 2705 jreq L506
1490 ; 527 TIM2->CR1 |= TIM2_CR1_UDIS;
1492 01d8 72125300 bset 21248,#1
1495 01dc 81 ret
1496 01dd L506:
1497 ; 531 TIM2->CR1 &= (u8)(~TIM2_CR1_UDIS);
1499 01dd 72135300 bres 21248,#1
1500 ; 533 }
1503 01e1 81 ret
1561 ; 552 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
1561 ; 553 {
1562 switch .text
1563 01e2 _TIM2_UpdateRequestConfig:
1567 ; 555 assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));
1569 ; 558 if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)
1571 01e2 4d tnz a
1572 01e3 2705 jreq L736
1573 ; 560 TIM2->CR1 |= TIM2_CR1_URS;
1575 01e5 72145300 bset 21248,#2
1578 01e9 81 ret
1579 01ea L736:
1580 ; 564 TIM2->CR1 &= (u8)(~TIM2_CR1_URS);
1582 01ea 72155300 bres 21248,#2
1583 ; 566 }
1586 01ee 81 ret
1643 ; 586 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
1643 ; 587 {
1644 switch .text
1645 01ef _TIM2_SelectOnePulseMode:
1649 ; 589 assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));
1651 ; 592 if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)
1653 01ef 4d tnz a
1654 01f0 2705 jreq L176
1655 ; 594 TIM2->CR1 |= TIM2_CR1_OPM;
1657 01f2 72165300 bset 21248,#3
1660 01f6 81 ret
1661 01f7 L176:
1662 ; 598 TIM2->CR1 &= (u8)(~TIM2_CR1_OPM);
1664 01f7 72175300 bres 21248,#3
1665 ; 601 }
1668 01fb 81 ret
1736 ; 641 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
1736 ; 642 TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
1736 ; 643 {
1737 switch .text
1738 01fc _TIM2_PrescalerConfig:
1742 ; 645 assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));
1744 ; 646 assert_param(IS_TIM2_PRESCALER_OK(Prescaler));
1746 ; 649 TIM2->PSCR = Prescaler;
1748 01fc 9e ld a,xh
1749 01fd c7530c ld 21260,a
1750 ; 652 TIM2->EGR = TIM2_PSCReloadMode;
1752 0200 9f ld a,xl
1753 0201 c75304 ld 21252,a
1754 ; 653 }
1757 0204 81 ret
1815 ; 673 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1815 ; 674 {
1816 switch .text
1817 0205 _TIM2_ForcedOC1Config:
1819 0205 88 push a
1820 00000000 OFST: set 0
1823 ; 676 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1825 ; 679 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1827 0206 c65305 ld a,21253
1828 0209 a48f and a,#143
1829 020b 1a01 or a,(OFST+1,sp)
1830 020d c75305 ld 21253,a
1831 ; 680 }
1834 0210 84 pop a
1835 0211 81 ret
1871 ; 700 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1871 ; 701 {
1872 switch .text
1873 0212 _TIM2_ForcedOC2Config:
1875 0212 88 push a
1876 00000000 OFST: set 0
1879 ; 703 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1881 ; 706 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1883 0213 c65306 ld a,21254
1884 0216 a48f and a,#143
1885 0218 1a01 or a,(OFST+1,sp)
1886 021a c75306 ld 21254,a
1887 ; 707 }
1890 021d 84 pop a
1891 021e 81 ret
1927 ; 727 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1927 ; 728 {
1928 switch .text
1929 021f _TIM2_ForcedOC3Config:
1931 021f 88 push a
1932 00000000 OFST: set 0
1935 ; 730 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1937 ; 733 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1939 0220 c65307 ld a,21255
1940 0223 a48f and a,#143
1941 0225 1a01 or a,(OFST+1,sp)
1942 0227 c75307 ld 21255,a
1943 ; 734 }
1946 022a 84 pop a
1947 022b 81 ret
1983 ; 752 void TIM2_ARRPreloadConfig(FunctionalState NewState)
1983 ; 753 {
1984 switch .text
1985 022c _TIM2_ARRPreloadConfig:
1989 ; 755 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1991 ; 758 if (NewState != DISABLE)
1993 022c 4d tnz a
1994 022d 2705 jreq L7201
1995 ; 760 TIM2->CR1 |= TIM2_CR1_ARPE;
1997 022f 721e5300 bset 21248,#7
2000 0233 81 ret
2001 0234 L7201:
2002 ; 764 TIM2->CR1 &= (u8)(~TIM2_CR1_ARPE);
2004 0234 721f5300 bres 21248,#7
2005 ; 766 }
2008 0238 81 ret
2044 ; 784 void TIM2_OC1PreloadConfig(FunctionalState NewState)
2044 ; 785 {
2045 switch .text
2046 0239 _TIM2_OC1PreloadConfig:
2050 ; 787 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2052 ; 790 if (NewState != DISABLE)
2054 0239 4d tnz a
2055 023a 2705 jreq L1501
2056 ; 792 TIM2->CCMR1 |= TIM2_CCMR_OCxPE;
2058 023c 72165305 bset 21253,#3
2061 0240 81 ret
2062 0241 L1501:
2063 ; 796 TIM2->CCMR1 &= (u8)(~TIM2_CCMR_OCxPE);
2065 0241 72175305 bres 21253,#3
2066 ; 798 }
2069 0245 81 ret
2105 ; 816 void TIM2_OC2PreloadConfig(FunctionalState NewState)
2105 ; 817 {
2106 switch .text
2107 0246 _TIM2_OC2PreloadConfig:
2111 ; 819 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2113 ; 822 if (NewState != DISABLE)
2115 0246 4d tnz a
2116 0247 2705 jreq L3701
2117 ; 824 TIM2->CCMR2 |= TIM2_CCMR_OCxPE;
2119 0249 72165306 bset 21254,#3
2122 024d 81 ret
2123 024e L3701:
2124 ; 828 TIM2->CCMR2 &= (u8)(~TIM2_CCMR_OCxPE);
2126 024e 72175306 bres 21254,#3
2127 ; 830 }
2130 0252 81 ret
2166 ; 848 void TIM2_OC3PreloadConfig(FunctionalState NewState)
2166 ; 849 {
2167 switch .text
2168 0253 _TIM2_OC3PreloadConfig:
2172 ; 851 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2174 ; 854 if (NewState != DISABLE)
2176 0253 4d tnz a
2177 0254 2705 jreq L5111
2178 ; 856 TIM2->CCMR3 |= TIM2_CCMR_OCxPE;
2180 0256 72165307 bset 21255,#3
2183 025a 81 ret
2184 025b L5111:
2185 ; 860 TIM2->CCMR3 &= (u8)(~TIM2_CCMR_OCxPE);
2187 025b 72175307 bres 21255,#3
2188 ; 862 }
2191 025f 81 ret
2264 ; 884 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
2264 ; 885 {
2265 switch .text
2266 0260 _TIM2_GenerateEvent:
2270 ; 887 assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
2272 ; 890 TIM2->EGR = TIM2_EventSource;
2274 0260 c75304 ld 21252,a
2275 ; 891 }
2278 0263 81 ret
2314 ; 911 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2314 ; 912 {
2315 switch .text
2316 0264 _TIM2_OC1PolarityConfig:
2320 ; 914 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2322 ; 917 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2324 0264 4d tnz a
2325 0265 2705 jreq L1711
2326 ; 919 TIM2->CCER1 |= TIM2_CCER1_CC1P;
2328 0267 72125308 bset 21256,#1
2331 026b 81 ret
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