📄 stm8s_i2c.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
47 ; 64 void I2C_DeInit(void)
47 ; 65 {
49 switch .text
50 0000 _I2C_DeInit:
54 ; 66 I2C->CR1 = I2C_CR1_RESET_VALUE;
56 0000 725f5210 clr 21008
57 ; 67 I2C->CR2 = I2C_CR2_RESET_VALUE;
59 0004 725f5211 clr 21009
60 ; 68 I2C->FREQR = I2C_FREQR_RESET_VALUE;
62 0008 725f5212 clr 21010
63 ; 69 I2C->OARL = I2C_OARL_RESET_VALUE;
65 000c 725f5213 clr 21011
66 ; 70 I2C->OARH = I2C_OARH_RESET_VALUE;
68 0010 725f5214 clr 21012
69 ; 71 I2C->ITR = I2C_ITR_RESET_VALUE;
71 0014 725f521a clr 21018
72 ; 72 I2C->CCRL = I2C_CCRL_RESET_VALUE;
74 0018 725f521b clr 21019
75 ; 73 I2C->CCRH = I2C_CCRH_RESET_VALUE;
77 001c 725f521c clr 21020
78 ; 74 I2C->TRISER = I2C_TRISER_RESET_VALUE;
80 0020 3502521d mov 21021,#2
81 ; 75 }
84 0024 81 ret
263 .const: section .text
264 0000 L01:
265 0000 000186a1 dc.l 100001
266 0004 L21:
267 0004 000f4240 dc.l 1000000
268 ; 99 void I2C_Init(u32 OutputClockFrequencyHz, u16 OwnAddress, I2C_DutyCycle_TypeDef DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, u8 InputClockFrequencyMHz )
268 ; 100 {
269 switch .text
270 0025 _I2C_Init:
272 0025 5209 subw sp,#9
273 00000009 OFST: set 9
276 ; 101 u16 result = 0x0004;
278 ; 102 u16 tmpval = 0;
280 ; 103 u8 tmpccrh = 0;
282 0027 0f07 clr (OFST-2,sp)
283 ; 106 assert_param(IS_I2C_ACK_OK(Ack));
285 ; 107 assert_param(IS_I2C_ADDMODE_OK(AddMode));
287 ; 108 assert_param(IS_I2C_OWN_ADDRESS_OK(OwnAddress));
289 ; 109 assert_param(IS_I2C_INPUT_CLOCK_FREQ_OK(InputClockFrequencyMHz));
291 ; 110 assert_param(IS_I2C_OUTPUT_CLOCK_FREQ_OK(OutputClockFrequencyHz));
293 ; 115 I2C->FREQR &= (u8)(~I2C_FREQR_FREQ);
295 0029 c65212 ld a,21010
296 002c a4c0 and a,#192
297 002e c75212 ld 21010,a
298 ; 117 I2C->FREQR |= InputClockFrequencyMHz;
300 0031 c65212 ld a,21010
301 0034 1a15 or a,(OFST+12,sp)
302 0036 c75212 ld 21010,a
303 ; 121 I2C->CR1 &= (u8)(~I2C_CR1_PE);
305 0039 72115210 bres 21008,#0
306 ; 124 I2C->CCRH &= (u8)(~(I2C_CCRH_FS | I2C_CCRH_DUTY | I2C_CCRH_CCR));
308 003d c6521c ld a,21020
309 0040 a430 and a,#48
310 0042 c7521c ld 21020,a
311 ; 125 I2C->CCRL &= (u8)(~I2C_CCRL_CCR);
313 0045 725f521b clr 21019
314 ; 128 if (OutputClockFrequencyHz > I2C_MAX_STANDARD_FREQ) /* FAST MODE */
316 0049 96 ldw x,sp
317 004a 1c000c addw x,#OFST+3
318 004d cd0000 call c_ltor
320 0050 ae0000 ldw x,#L01
321 0053 cd0000 call c_lcmp
323 0056 257c jrult L131
324 ; 131 tmpccrh = I2C_CCRH_FS;
326 0058 a680 ld a,#128
327 005a 6b07 ld (OFST-2,sp),a
328 ; 133 if (DutyCycle == I2C_DUTYCYCLE_2)
330 005c 96 ldw x,sp
331 005d 0d12 tnz (OFST+9,sp)
332 005f 262b jrne L331
333 ; 136 result = (u16) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 3));
335 0061 1c000c addw x,#OFST+3
336 0064 cd0000 call c_ltor
338 0067 a603 ld a,#3
339 0069 cd0000 call c_smul
341 006c 96 ldw x,sp
342 006d 5c incw x
343 006e cd0000 call c_rtol
345 0071 7b15 ld a,(OFST+12,sp)
346 0073 b703 ld c_lreg+3,a
347 0075 3f02 clr c_lreg+2
348 0077 3f01 clr c_lreg+1
349 0079 3f00 clr c_lreg
350 007b ae0004 ldw x,#L21
351 007e cd0000 call c_lmul
353 0081 96 ldw x,sp
354 0082 5c incw x
355 0083 cd0000 call c_ludv
357 0086 be02 ldw x,c_lreg+2
358 0088 1f08 ldw (OFST-1,sp),x
360 008a 202f jra L531
361 008c L331:
362 ; 141 result = (u16) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 25));
364 008c 1c000c addw x,#OFST+3
365 008f cd0000 call c_ltor
367 0092 a619 ld a,#25
368 0094 cd0000 call c_smul
370 0097 96 ldw x,sp
371 0098 5c incw x
372 0099 cd0000 call c_rtol
374 009c 7b15 ld a,(OFST+12,sp)
375 009e b703 ld c_lreg+3,a
376 00a0 3f02 clr c_lreg+2
377 00a2 3f01 clr c_lreg+1
378 00a4 3f00 clr c_lreg
379 00a6 ae0004 ldw x,#L21
380 00a9 cd0000 call c_lmul
382 00ac 96 ldw x,sp
383 00ad 5c incw x
384 00ae cd0000 call c_ludv
386 00b1 be02 ldw x,c_lreg+2
387 00b3 1f08 ldw (OFST-1,sp),x
388 ; 143 tmpccrh |= I2C_CCRH_DUTY;
390 00b5 7b07 ld a,(OFST-2,sp)
391 00b7 aa40 or a,#64
392 00b9 6b07 ld (OFST-2,sp),a
393 00bb L531:
394 ; 147 if (result < (u16)0x01)
396 00bb 1e08 ldw x,(OFST-1,sp)
397 00bd 2603 jrne L731
398 ; 150 result = (u16)0x0001;
400 00bf 5c incw x
401 00c0 1f08 ldw (OFST-1,sp),x
402 00c2 L731:
403 ; 156 tmpval = ((InputClockFrequencyMHz * 3) / 10) + 1;
405 00c2 7b15 ld a,(OFST+12,sp)
406 00c4 97 ld xl,a
407 00c5 a603 ld a,#3
408 00c7 42 mul x,a
409 00c8 a60a ld a,#10
410 00ca cd0000 call c_sdivx
412 00cd 5c incw x
413 00ce 1f05 ldw (OFST-4,sp),x
414 ; 157 I2C->TRISER = (u8)tmpval;
416 00d0 7b06 ld a,(OFST-3,sp)
418 00d2 2038 jra L141
419 00d4 L131:
420 ; 164 result = (u16)((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz << (u8)1));
422 00d4 96 ldw x,sp
423 00d5 1c000c addw x,#OFST+3
424 00d8 cd0000 call c_ltor
426 00db 3803 sll c_lreg+3
427 00dd 3902 rlc c_lreg+2
428 00df 3901 rlc c_lreg+1
429 00e1 96 ldw x,sp
430 00e2 3900 rlc c_lreg
431 00e4 5c incw x
432 00e5 cd0000 call c_rtol
434 00e8 7b15 ld a,(OFST+12,sp)
435 00ea b703 ld c_lreg+3,a
436 00ec 3f02 clr c_lreg+2
437 00ee 3f01 clr c_lreg+1
438 00f0 3f00 clr c_lreg
439 00f2 ae0004 ldw x,#L21
440 00f5 cd0000 call c_lmul
442 00f8 96 ldw x,sp
443 00f9 5c incw x
444 00fa cd0000 call c_ludv
446 00fd be02 ldw x,c_lreg+2
447 ; 167 if (result < (u16)0x0004)
449 00ff a30004 cpw x,#4
450 0102 2403 jruge L341
451 ; 170 result = (u16)0x0004;
453 0104 ae0004 ldw x,#4
454 0107 L341:
455 0107 1f08 ldw (OFST-1,sp),x
456 ; 176 I2C->TRISER = (u8)(InputClockFrequencyMHz + 1);
458 0109 7b15 ld a,(OFST+12,sp)
459 010b 4c inc a
460 010c L141:
461 010c c7521d ld 21021,a
462 ; 181 I2C->CCRL = (u8)result;
464 010f 7b09 ld a,(OFST+0,sp)
465 0111 c7521b ld 21019,a
466 ; 182 I2C->CCRH = (u8)(((u8)(result >> 8) & I2C_CCRH_CCR) | tmpccrh);
468 0114 7b08 ld a,(OFST-1,sp)
469 0116 a40f and a,#15
470 0118 1a07 or a,(OFST-2,sp)
471 011a c7521c ld 21020,a
472 ; 185 I2C->CR1 |= I2C_CR1_PE;
474 011d 72105210 bset 21008,#0
475 ; 188 I2C_AcknowledgeConfig(Ack);
477 0121 7b13 ld a,(OFST+10,sp)
478 0123 ad6d call _I2C_AcknowledgeConfig
480 ; 191 I2C->OARL = (u8)(OwnAddress);
482 0125 7b11 ld a,(OFST+8,sp)
483 0127 c75213 ld 21011,a
484 ; 192 I2C->OARH = (u8)((u8)AddMode |
484 ; 193 I2C_OARH_ADDCONF |
484 ; 194 (u8)((OwnAddress & (u16)0x0300) >> (u8)7));
486 012a 7b10 ld a,(OFST+7,sp)
487 012c a403 and a,#3
488 012e 97 ld xl,a
489 012f 4f clr a
490 0130 02 rlwa x,a
491 0131 4f clr a
492 0132 01 rrwa x,a
493 0133 48 sll a
494 0134 59 rlcw x
495 0135 9f ld a,xl
496 0136 6b04 ld (OFST-5,sp),a
497 0138 7b14 ld a,(OFST+11,sp)
498 013a aa40 or a,#64
499 013c 1a04 or a,(OFST-5,sp)
500 013e c75214 ld 21012,a
501 ; 195 }
504 0141 5b09 addw sp,#9
505 0143 81 ret
560 ; 212 void I2C_Cmd(FunctionalState NewState)
560 ; 213 {
561 switch .text
562 0144 _I2C_Cmd:
566 ; 216 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
568 ; 218 if (NewState != DISABLE)
570 0144 4d tnz a
571 0145 2705 jreq L371
572 ; 221 I2C->CR1 |= I2C_CR1_PE;
574 0147 72105210 bset 21008,#0
577 014b 81 ret
578 014c L371:
579 ; 226 I2C->CR1 &= (u8)(~I2C_CR1_PE);
581 014c 72115210 bres 21008,#0
582 ; 228 }
585 0150 81 ret
620 ; 245 void I2C_GeneralCallCmd(FunctionalState NewState)
620 ; 246 {
621 switch .text
622 0151 _I2C_GeneralCallCmd:
626 ; 249 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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