📄 stm8s_clk.ls
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1867 021e 1a01 or a,(OFST+1,sp)
1868 0220 c750cb ld 20683,a
1869 ; 698 }
1872 0223 84 pop a
1873 0224 81 ret
1897 ; 715 void CLK_ClockSecuritySystemEnable(void)
1897 ; 716 {
1898 switch .text
1899 0225 _CLK_ClockSecuritySystemEnable:
1903 ; 718 CLK->CSSR |= CLK_CSSR_CSSEN;
1905 0225 721050c8 bset 20680,#0
1906 ; 719 }
1909 0229 81 ret
1934 ; 736 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
1934 ; 737 {
1935 switch .text
1936 022a _CLK_GetSYSCLKSource:
1940 ; 738 return((CLK_Source_TypeDef)CLK->CMSR);
1942 022a c650c3 ld a,20675
1945 022d 81 ret
2008 ; 756 u32 CLK_GetClockFreq(void)
2008 ; 757 {
2009 switch .text
2010 022e _CLK_GetClockFreq:
2012 022e 5209 subw sp,#9
2013 00000009 OFST: set 9
2016 ; 759 u32 clockfrequency = 0;
2018 ; 760 CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
2020 ; 761 u8 tmp = 0, presc = 0;
2024 ; 764 clocksource = (CLK_Source_TypeDef)CLK->CMSR;
2026 0230 c650c3 ld a,20675
2027 0233 6b09 ld (OFST+0,sp),a
2028 ; 766 if (clocksource == CLK_SOURCE_HSI)
2030 0235 a1e1 cp a,#225
2031 0237 2634 jrne L3011
2032 ; 768 tmp = (u8)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
2034 0239 c650c6 ld a,20678
2035 023c a418 and a,#24
2036 023e 44 srl a
2037 023f 44 srl a
2038 0240 44 srl a
2039 ; 769 tmp = (u8)(tmp >> 3);
2041 ; 770 presc = HSIDivFactor[tmp];
2043 0241 5f clrw x
2044 0242 97 ld xl,a
2045 0243 d60000 ld a,(_HSIDivFactor,x)
2046 0246 6b09 ld (OFST+0,sp),a
2047 ; 771 clockfrequency = HSI_VALUE / presc;
2049 0248 b703 ld c_lreg+3,a
2050 024a 3f02 clr c_lreg+2
2051 024c 3f01 clr c_lreg+1
2052 024e 3f00 clr c_lreg
2053 0250 96 ldw x,sp
2054 0251 5c incw x
2055 0252 cd0000 call c_rtol
2057 0255 ae2400 ldw x,#9216
2058 0258 bf02 ldw c_lreg+2,x
2059 025a ae00f4 ldw x,#244
2060 025d bf00 ldw c_lreg,x
2061 025f 96 ldw x,sp
2062 0260 5c incw x
2063 0261 cd0000 call c_ludv
2065 0264 96 ldw x,sp
2066 0265 1c0005 addw x,#OFST-4
2067 0268 cd0000 call c_rtol
2070 026b 2018 jra L5011
2071 026d L3011:
2072 ; 773 else if ( clocksource == CLK_SOURCE_LSI)
2074 026d a1d2 cp a,#210
2075 026f 260a jrne L7011
2076 ; 775 clockfrequency = LSI_VALUE;
2078 0271 aef400 ldw x,#62464
2079 0274 1f07 ldw (OFST-2,sp),x
2080 0276 ae0001 ldw x,#1
2082 0279 2008 jp LC004
2083 027b L7011:
2084 ; 779 clockfrequency = HSE_VALUE;
2086 027b ae3600 ldw x,#13824
2087 027e 1f07 ldw (OFST-2,sp),x
2088 0280 ae016e ldw x,#366
2089 0283 LC004:
2090 0283 1f05 ldw (OFST-4,sp),x
2091 0285 L5011:
2092 ; 782 return((u32)clockfrequency);
2094 0285 96 ldw x,sp
2095 0286 1c0005 addw x,#OFST-4
2096 0289 cd0000 call c_ltor
2100 028c 5b09 addw sp,#9
2101 028e 81 ret
2200 ; 800 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
2200 ; 801 {
2201 switch .text
2202 028f _CLK_AdjustHSICalibrationValue:
2204 028f 88 push a
2205 00000000 OFST: set 0
2208 ; 804 assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
2210 ; 807 CLK->HSITRIMR = (u8)((CLK->HSITRIMR & (u8)(~CLK_HSITRIMR_HSITRIM))|((u8)CLK_HSICalibrationValue));
2212 0290 c650cc ld a,20684
2213 0293 a4f8 and a,#248
2214 0295 1a01 or a,(OFST+1,sp)
2215 0297 c750cc ld 20684,a
2216 ; 809 }
2219 029a 84 pop a
2220 029b 81 ret
2244 ; 828 void CLK_SYSCLKEmergencyClear(void)
2244 ; 829 {
2245 switch .text
2246 029c _CLK_SYSCLKEmergencyClear:
2250 ; 830 CLK->SWCR &= (u8)(~CLK_SWCR_SWBSY);
2252 029c 721150c5 bres 20677,#0
2253 ; 831 }
2256 02a0 81 ret
2409 ; 847 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
2409 ; 848 {
2410 switch .text
2411 02a1 _CLK_GetFlagStatus:
2413 02a1 89 pushw x
2414 02a2 5203 subw sp,#3
2415 00000003 OFST: set 3
2418 ; 850 u16 statusreg = 0;
2420 ; 851 u8 tmpreg = 0;
2422 ; 852 FlagStatus bitstatus = RESET;
2424 ; 855 assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
2426 ; 858 statusreg = (u16)((u16)CLK_FLAG & (u16)0xFF00);
2428 02a4 01 rrwa x,a
2429 02a5 4f clr a
2430 02a6 02 rlwa x,a
2431 02a7 1f01 ldw (OFST-2,sp),x
2432 ; 861 if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
2434 02a9 a30100 cpw x,#256
2435 02ac 2605 jrne L5521
2436 ; 863 tmpreg = CLK->ICKR;
2438 02ae c650c0 ld a,20672
2440 02b1 2021 jra L7521
2441 02b3 L5521:
2442 ; 865 else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
2444 02b3 a30200 cpw x,#512
2445 02b6 2605 jrne L1621
2446 ; 867 tmpreg = CLK->ECKR;
2448 02b8 c650c1 ld a,20673
2450 02bb 2017 jra L7521
2451 02bd L1621:
2452 ; 869 else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
2454 02bd a30300 cpw x,#768
2455 02c0 2605 jrne L5621
2456 ; 871 tmpreg = CLK->SWCR;
2458 02c2 c650c5 ld a,20677
2460 02c5 200d jra L7521
2461 02c7 L5621:
2462 ; 873 else if (statusreg == 0x0400) /* The flag to check is in CSS register */
2464 02c7 a30400 cpw x,#1024
2465 02ca 2605 jrne L1721
2466 ; 875 tmpreg = CLK->CSSR;
2468 02cc c650c8 ld a,20680
2470 02cf 2003 jra L7521
2471 02d1 L1721:
2472 ; 879 tmpreg = CLK->CCOR;
2474 02d1 c650c9 ld a,20681
2475 02d4 L7521:
2476 02d4 6b03 ld (OFST+0,sp),a
2477 ; 882 if ((tmpreg & (u8)CLK_FLAG) != (u8)RESET)
2479 02d6 7b05 ld a,(OFST+2,sp)
2480 02d8 1503 bcp a,(OFST+0,sp)
2481 02da 2704 jreq L5721
2482 ; 884 bitstatus = SET;
2484 02dc a601 ld a,#1
2486 02de 2001 jra L7721
2487 02e0 L5721:
2488 ; 888 bitstatus = RESET;
2490 02e0 4f clr a
2491 02e1 L7721:
2492 ; 892 return((FlagStatus)bitstatus);
2496 02e1 5b05 addw sp,#5
2497 02e3 81 ret
2543 ; 913 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2543 ; 914 {
2544 switch .text
2545 02e4 _CLK_GetITStatus:
2547 02e4 88 push a
2548 02e5 88 push a
2549 00000001 OFST: set 1
2552 ; 916 ITStatus bitstatus = RESET;
2554 ; 919 assert_param(IS_CLK_IT_OK(CLK_IT));
2556 ; 921 if (CLK_IT == CLK_IT_SWIF)
2558 02e6 a11c cp a,#28
2559 02e8 2609 jrne L3231
2560 ; 924 if ((CLK->SWCR & (u8)CLK_IT) == (u8)0x0C)
2562 02ea c450c5 and a,20677
2563 02ed a10c cp a,#12
2564 02ef 260f jrne L3331
2565 ; 926 bitstatus = SET;
2567 02f1 2009 jp LC006
2568 ; 930 bitstatus = RESET;
2569 02f3 L3231:
2570 ; 936 if ((CLK->CSSR & (u8)CLK_IT) == (u8)0x0C)
2572 02f3 c650c8 ld a,20680
2573 02f6 1402 and a,(OFST+1,sp)
2574 02f8 a10c cp a,#12
2575 02fa 2604 jrne L3331
2576 ; 938 bitstatus = SET;
2578 02fc LC006:
2580 02fc a601 ld a,#1
2582 02fe 2001 jra L1331
2583 0300 L3331:
2584 ; 942 bitstatus = RESET;
2587 0300 4f clr a
2588 0301 L1331:
2589 ; 947 return bitstatus;
2593 0301 85 popw x
2594 0302 81 ret
2630 ; 966 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2630 ; 967 {
2631 switch .text
2632 0303 _CLK_ClearITPendingBit:
2636 ; 970 assert_param(IS_CLK_IT_OK(CLK_IT));
2638 ; 972 if (CLK_IT == (u8)CLK_IT_CSSD)
2640 0303 a10c cp a,#12
2641 0305 2605 jrne L5531
2642 ; 975 CLK->CSSR &= (u8)(~CLK_CSSR_CSSD);
2644 0307 721750c8 bres 20680,#3
2647 030b 81 ret
2648 030c L5531:
2649 ; 980 CLK->SWCR &= (u8)(~CLK_SWCR_SWIF);
2651 030c 721750c5 bres 20677,#3
2652 ; 983 }
2655 0310 81 ret
2690 xdef _CLKPrescTable
2691 xdef _HSIDivFactor
2692 xdef _CLK_ClearITPendingBit
2693 xdef _CLK_GetITStatus
2694 xdef _CLK_GetFlagStatus
2695 xdef _CLK_GetSYSCLKSource
2696 xdef _CLK_GetClockFreq
2697 xdef _CLK_AdjustHSICalibrationValue
2698 xdef _CLK_SYSCLKEmergencyClear
2699 xdef _CLK_ClockSecuritySystemEnable
2700 xdef _CLK_CANConfig
2701 xdef _CLK_SWIMConfig
2702 xdef _CLK_SYSCLKConfig
2703 xdef _CLK_ITConfig
2704 xdef _CLK_CCOConfig
2705 xdef _CLK_HSIPrescalerConfig
2706 xdef _CLK_ClockSwitchConfig
2707 xdef _CLK_PeripheralClockConfig
2708 xdef _CLK_SlowActiveHaltWakeUpCmd
2709 xdef _CLK_FastHaltWakeUpCmd
2710 xdef _CLK_ClockSwitchCmd
2711 xdef _CLK_CCOCmd
2712 xdef _CLK_LSICmd
2713 xdef _CLK_HSICmd
2714 xdef _CLK_HSECmd
2715 xdef _CLK_DeInit
2716 xref.b c_lreg
2717 xref.b c_x
2736 xref c_ltor
2737 xref c_ludv
2738 xref c_rtol
2739 end
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