📄 stm8s_clk.ls
字号:
989 00fb 89 pushw x
990 00fc 5204 subw sp,#4
991 00000004 OFST: set 4
994 ; 409 u16 DownCounter = CLK_TIMEOUT;
996 00fe ae0491 ldw x,#1169
997 0101 1f03 ldw (OFST-1,sp),x
998 ; 410 ErrorStatus Swif = ERROR;
1000 ; 413 assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
1002 ; 414 assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
1004 ; 415 assert_param(IS_FUNCTIONALSTATE_OK(CLK_SwitchIT));
1006 ; 416 assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
1008 ; 419 clock_master = (CLK_Source_TypeDef)CLK->CMSR;
1010 0103 c650c3 ld a,20675
1011 0106 6b01 ld (OFST-3,sp),a
1012 ; 422 if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
1014 0108 7b05 ld a,(OFST+1,sp)
1015 010a 4a dec a
1016 010b 262d jrne L734
1017 ; 426 CLK->SWCR |= CLK_SWCR_SWEN;
1019 010d 721250c5 bset 20677,#1
1020 ; 429 if (CLK_SwitchIT != DISABLE)
1022 0111 7b09 ld a,(OFST+5,sp)
1023 0113 2706 jreq L144
1024 ; 431 CLK->SWCR |= CLK_SWCR_SWIEN;
1026 0115 721450c5 bset 20677,#2
1028 0119 2004 jra L344
1029 011b L144:
1030 ; 435 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1032 011b 721550c5 bres 20677,#2
1033 011f L344:
1034 ; 439 CLK->SWR = (u8)CLK_NewClock;
1036 011f 7b06 ld a,(OFST+2,sp)
1037 0121 c750c4 ld 20676,a
1039 0124 2003 jra L154
1040 0126 L544:
1041 ; 443 DownCounter--;
1043 0126 5a decw x
1044 0127 1f03 ldw (OFST-1,sp),x
1045 0129 L154:
1046 ; 441 while (((CLK->SWCR & CLK_SWCR_SWBSY) && (DownCounter != 0)))
1048 0129 720150c504 btjf 20677,#0,L554
1050 012e 1e03 ldw x,(OFST-1,sp)
1051 0130 26f4 jrne L544
1052 0132 L554:
1053 ; 446 if (DownCounter != 0)
1055 0132 1e03 ldw x,(OFST-1,sp)
1056 ; 448 Swif = SUCCESS;
1058 0134 2617 jrne LC003
1059 ; 452 Swif = ERROR;
1061 0136 0f02 clr (OFST-2,sp)
1062 0138 2017 jra L364
1063 013a L734:
1064 ; 460 if (CLK_SwitchIT != DISABLE)
1066 013a 7b09 ld a,(OFST+5,sp)
1067 013c 2706 jreq L564
1068 ; 462 CLK->SWCR |= CLK_SWCR_SWIEN;
1070 013e 721450c5 bset 20677,#2
1072 0142 2004 jra L764
1073 0144 L564:
1074 ; 466 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1076 0144 721550c5 bres 20677,#2
1077 0148 L764:
1078 ; 470 CLK->SWR = (u8)CLK_NewClock;
1080 0148 7b06 ld a,(OFST+2,sp)
1081 014a c750c4 ld 20676,a
1082 ; 474 Swif = SUCCESS;
1084 014d LC003:
1086 014d a601 ld a,#1
1087 014f 6b02 ld (OFST-2,sp),a
1088 0151 L364:
1089 ; 479 if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
1091 0151 7b0a ld a,(OFST+6,sp)
1092 0153 260c jrne L174
1094 0155 7b01 ld a,(OFST-3,sp)
1095 0157 a1e1 cp a,#225
1096 0159 2606 jrne L174
1097 ; 481 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
1099 015b 721150c0 bres 20672,#0
1101 015f 201e jra L374
1102 0161 L174:
1103 ; 483 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
1105 0161 7b0a ld a,(OFST+6,sp)
1106 0163 260c jrne L574
1108 0165 7b01 ld a,(OFST-3,sp)
1109 0167 a1d2 cp a,#210
1110 0169 2606 jrne L574
1111 ; 485 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
1113 016b 721750c0 bres 20672,#3
1115 016f 200e jra L374
1116 0171 L574:
1117 ; 487 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
1119 0171 7b0a ld a,(OFST+6,sp)
1120 0173 260a jrne L374
1122 0175 7b01 ld a,(OFST-3,sp)
1123 0177 a1b4 cp a,#180
1124 0179 2604 jrne L374
1125 ; 489 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
1127 017b 721150c1 bres 20673,#0
1128 017f L374:
1129 ; 492 return(Swif);
1131 017f 7b02 ld a,(OFST-2,sp)
1134 0181 5b06 addw sp,#6
1135 0183 81 ret
1273 ; 509 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
1273 ; 510 {
1274 switch .text
1275 0184 _CLK_HSIPrescalerConfig:
1277 0184 88 push a
1278 00000000 OFST: set 0
1281 ; 513 assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
1283 ; 516 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1285 0185 c650c6 ld a,20678
1286 0188 a4e7 and a,#231
1287 018a c750c6 ld 20678,a
1288 ; 519 CLK->CKDIVR |= (u8)HSIPrescaler;
1290 018d c650c6 ld a,20678
1291 0190 1a01 or a,(OFST+1,sp)
1292 0192 c750c6 ld 20678,a
1293 ; 521 }
1296 0195 84 pop a
1297 0196 81 ret
1432 ; 539 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
1432 ; 540 {
1433 switch .text
1434 0197 _CLK_CCOConfig:
1436 0197 88 push a
1437 00000000 OFST: set 0
1440 ; 543 assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
1442 ; 546 CLK->CCOR &= (u8)(~CLK_CCOR_CCOSEL);
1444 0198 c650c9 ld a,20681
1445 019b a4e1 and a,#225
1446 019d c750c9 ld 20681,a
1447 ; 549 CLK->CCOR |= (u8)CLK_CCO;
1449 01a0 c650c9 ld a,20681
1450 01a3 1a01 or a,(OFST+1,sp)
1451 01a5 c750c9 ld 20681,a
1452 ; 552 CLK->CCOR |= CLK_CCOR_CCOEN;
1454 ; 554 }
1457 01a8 84 pop a
1458 01a9 721050c9 bset 20681,#0
1459 01ad 81 ret
1524 ; 571 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState IT_NewState)
1524 ; 572 {
1525 switch .text
1526 01ae _CLK_ITConfig:
1528 01ae 89 pushw x
1529 00000000 OFST: set 0
1532 ; 575 assert_param(IS_FUNCTIONALSTATE_OK(IT_NewState));
1534 ; 576 assert_param(IS_CLK_IT_OK(CLK_IT));
1536 ; 578 if (IT_NewState != DISABLE)
1538 01af 9f ld a,xl
1539 01b0 4d tnz a
1540 01b1 2715 jreq L776
1541 ; 580 switch (CLK_IT)
1543 01b3 9e ld a,xh
1545 ; 588 default:
1545 ; 589 break;
1546 01b4 a00c sub a,#12
1547 01b6 270a jreq L336
1548 01b8 a010 sub a,#16
1549 01ba 2620 jrne L507
1550 ; 582 case CLK_IT_SWIF: /* Enable the clock switch interrupt */
1550 ; 583 CLK->SWCR |= CLK_SWCR_SWIEN;
1552 01bc 721450c5 bset 20677,#2
1553 ; 584 break;
1555 01c0 201a jra L507
1556 01c2 L336:
1557 ; 585 case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
1557 ; 586 CLK->CSSR |= CLK_CSSR_CSSDIE;
1559 01c2 721450c8 bset 20680,#2
1560 ; 587 break;
1562 01c6 2014 jra L507
1563 ; 588 default:
1563 ; 589 break;
1566 01c8 L776:
1567 ; 594 switch (CLK_IT)
1569 01c8 7b01 ld a,(OFST+1,sp)
1571 ; 602 default:
1571 ; 603 break;
1572 01ca a00c sub a,#12
1573 01cc 270a jreq L146
1574 01ce a010 sub a,#16
1575 01d0 260a jrne L507
1576 ; 596 case CLK_IT_SWIF: /* Disable the clock switch interrupt */
1576 ; 597 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1578 01d2 721550c5 bres 20677,#2
1579 ; 598 break;
1581 01d6 2004 jra L507
1582 01d8 L146:
1583 ; 599 case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
1583 ; 600 CLK->CSSR &= (u8)(~CLK_CSSR_CSSDIE);
1585 01d8 721550c8 bres 20680,#2
1586 ; 601 break;
1587 01dc L507:
1588 ; 607 }
1591 01dc 85 popw x
1592 01dd 81 ret
1593 ; 602 default:
1593 ; 603 break;
1629 ; 623 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef ClockPrescaler)
1629 ; 624 {
1630 switch .text
1631 01de _CLK_SYSCLKConfig:
1633 01de 88 push a
1634 00000000 OFST: set 0
1637 ; 627 assert_param(IS_CLK_PRESCALER_OK(ClockPrescaler));
1639 ; 629 if (((u8)ClockPrescaler & (u8)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
1641 01df a580 bcp a,#128
1642 01e1 260e jrne L137
1643 ; 631 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1645 01e3 c650c6 ld a,20678
1646 01e6 a4e7 and a,#231
1647 01e8 c750c6 ld 20678,a
1648 ; 632 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_HSIDIV);
1650 01eb 7b01 ld a,(OFST+1,sp)
1651 01ed a418 and a,#24
1653 01ef 200c jra L337
1654 01f1 L137:
1655 ; 636 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_CPUDIV);
1657 01f1 c650c6 ld a,20678
1658 01f4 a4f8 and a,#248
1659 01f6 c750c6 ld 20678,a
1660 ; 637 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_CPUDIV);
1662 01f9 7b01 ld a,(OFST+1,sp)
1663 01fb a407 and a,#7
1664 01fd L337:
1665 01fd ca50c6 or a,20678
1666 0200 c750c6 ld 20678,a
1667 ; 640 }
1670 0203 84 pop a
1671 0204 81 ret
1727 ; 654 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
1727 ; 655 {
1728 switch .text
1729 0205 _CLK_SWIMConfig:
1733 ; 658 assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
1735 ; 660 if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
1737 0205 4d tnz a
1738 0206 2705 jreq L367
1739 ; 663 CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
1741 0208 721050cd bset 20685,#0
1744 020c 81 ret
1745 020d L367:
1746 ; 668 CLK->SWIMCCR &= (u8)(~CLK_SWIMCCR_SWIMDIV);
1748 020d 721150cd bres 20685,#0
1749 ; 671 }
1752 0211 81 ret
1849 ; 686 void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider)
1849 ; 687 {
1850 switch .text
1851 0212 _CLK_CANConfig:
1853 0212 88 push a
1854 00000000 OFST: set 0
1857 ; 690 assert_param(IS_CLK_CANDIVIDER_OK(CLK_CANDivider));
1859 ; 693 CLK->CANCCR &= (u8)(~CLK_CANCCR_CANDIV);
1861 0213 c650cb ld a,20683
1862 0216 a4f8 and a,#248
1863 0218 c750cb ld 20683,a
1864 ; 696 CLK->CANCCR |= (u8)CLK_CANDivider;
1866 021b c650cb ld a,20683
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