📄 stm8s_clk.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
19 .const: section .text
20 0000 _HSIDivFactor:
21 0000 01 dc.b 1
22 0001 02 dc.b 2
23 0002 04 dc.b 4
24 0003 08 dc.b 8
25 0004 _CLKPrescTable:
26 0004 01 dc.b 1
27 0005 02 dc.b 2
28 0006 04 dc.b 4
29 0007 08 dc.b 8
30 0008 0a dc.b 10
31 0009 10 dc.b 16
32 000a 14 dc.b 20
33 000b 28 dc.b 40
62 ; 83 void CLK_DeInit(void)
62 ; 84 {
64 switch .text
65 0000 _CLK_DeInit:
69 ; 86 CLK->ICKR = CLK_ICKR_RESET_VALUE;
71 0000 350150c0 mov 20672,#1
72 ; 87 CLK->ECKR = CLK_ECKR_RESET_VALUE;
74 0004 725f50c1 clr 20673
75 ; 88 CLK->SWR = CLK_SWR_RESET_VALUE;
77 0008 35e150c4 mov 20676,#225
78 ; 89 CLK->SWCR = CLK_SWCR_RESET_VALUE;
80 000c 725f50c5 clr 20677
81 ; 90 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
83 0010 351850c6 mov 20678,#24
84 ; 91 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
86 0014 35ff50c7 mov 20679,#255
87 ; 92 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
89 0018 35ff50ca mov 20682,#255
90 ; 93 CLK->CSSR = CLK_CSSR_RESET_VALUE;
92 001c 725f50c8 clr 20680
93 ; 95 CLK->CCOR = CLK_CCOR_RESET_VALUE;
95 0020 725f50c9 clr 20681
97 0024 L52:
98 ; 96 while (CLK->CCOR & CLK_CCOR_CCOEN)
100 0024 720050c9fb btjt 20681,#0,L52
101 ; 98 CLK->CCOR = CLK_CCOR_RESET_VALUE;
103 0029 725f50c9 clr 20681
104 ; 100 CLK->CANCCR = CLK_CANCCR_RESET_VALUE;
106 002d 725f50cb clr 20683
107 ; 101 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
109 0031 725f50cc clr 20684
110 ; 102 CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
112 0035 725f50cd clr 20685
113 ; 104 }
116 0039 81 ret
172 ; 123 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
172 ; 124 {
173 switch .text
174 003a _CLK_FastHaltWakeUpCmd:
178 ; 127 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
180 ; 129 if (NewState != DISABLE)
182 003a 4d tnz a
183 003b 2705 jreq L75
184 ; 132 CLK->ICKR |= CLK_ICKR_FHWU;
186 003d 721450c0 bset 20672,#2
189 0041 81 ret
190 0042 L75:
191 ; 137 CLK->ICKR &= (u8)(~CLK_ICKR_FHWU);
193 0042 721550c0 bres 20672,#2
194 ; 140 }
197 0046 81 ret
232 ; 154 void CLK_HSECmd(FunctionalState CLK_NewState)
232 ; 155 {
233 switch .text
234 0047 _CLK_HSECmd:
238 ; 158 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
240 ; 160 if (CLK_NewState != DISABLE)
242 0047 4d tnz a
243 0048 2705 jreq L101
244 ; 163 CLK->ECKR |= CLK_ECKR_HSEEN;
246 004a 721050c1 bset 20673,#0
249 004e 81 ret
250 004f L101:
251 ; 168 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
253 004f 721150c1 bres 20673,#0
254 ; 171 }
257 0053 81 ret
292 ; 185 void CLK_HSICmd(FunctionalState CLK_NewState)
292 ; 186 {
293 switch .text
294 0054 _CLK_HSICmd:
298 ; 189 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
300 ; 191 if (CLK_NewState != DISABLE)
302 0054 4d tnz a
303 0055 2705 jreq L321
304 ; 194 CLK->ICKR |= CLK_ICKR_HSIEN;
306 0057 721050c0 bset 20672,#0
309 005b 81 ret
310 005c L321:
311 ; 199 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
313 005c 721150c0 bres 20672,#0
314 ; 202 }
317 0060 81 ret
352 ; 216 void CLK_LSICmd(FunctionalState CLK_NewState)
352 ; 217 {
353 switch .text
354 0061 _CLK_LSICmd:
358 ; 220 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
360 ; 222 if (CLK_NewState != DISABLE)
362 0061 4d tnz a
363 0062 2705 jreq L541
364 ; 225 CLK->ICKR |= CLK_ICKR_LSIEN;
366 0064 721650c0 bset 20672,#3
369 0068 81 ret
370 0069 L541:
371 ; 230 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
373 0069 721750c0 bres 20672,#3
374 ; 233 }
377 006d 81 ret
412 ; 248 void CLK_CCOCmd(FunctionalState CLK_NewState)
412 ; 249 {
413 switch .text
414 006e _CLK_CCOCmd:
418 ; 252 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
420 ; 254 if (CLK_NewState != DISABLE)
422 006e 4d tnz a
423 006f 2705 jreq L761
424 ; 257 CLK->CCOR |= CLK_CCOR_CCOEN;
426 0071 721050c9 bset 20681,#0
429 0075 81 ret
430 0076 L761:
431 ; 262 CLK->CCOR &= (u8)(~CLK_CCOR_CCOEN);
433 0076 721150c9 bres 20681,#0
434 ; 265 }
437 007a 81 ret
472 ; 281 void CLK_ClockSwitchCmd(FunctionalState CLK_NewState)
472 ; 282 {
473 switch .text
474 007b _CLK_ClockSwitchCmd:
478 ; 285 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
480 ; 287 if (CLK_NewState != DISABLE )
482 007b 4d tnz a
483 007c 2705 jreq L112
484 ; 290 CLK->SWCR |= CLK_SWCR_SWEN;
486 007e 721250c5 bset 20677,#1
489 0082 81 ret
490 0083 L112:
491 ; 295 CLK->SWCR &= (u8)(~CLK_SWCR_SWEN);
493 0083 721350c5 bres 20677,#1
494 ; 298 }
497 0087 81 ret
533 ; 315 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
533 ; 316 {
534 switch .text
535 0088 _CLK_SlowActiveHaltWakeUpCmd:
539 ; 319 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
541 ; 321 if (NewState != DISABLE)
543 0088 4d tnz a
544 0089 2705 jreq L332
545 ; 324 CLK->ICKR |= CLK_ICKR_SWUAH;
547 008b 721a50c0 bset 20672,#5
550 008f 81 ret
551 0090 L332:
552 ; 329 CLK->ICKR &= (u8)(~CLK_ICKR_SWUAH);
554 0090 721b50c0 bres 20672,#5
555 ; 332 }
558 0094 81 ret
693 ; 349 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState CLK_NewState)
693 ; 350 {
694 switch .text
695 0095 _CLK_PeripheralClockConfig:
697 0095 89 pushw x
698 00000000 OFST: set 0
701 ; 353 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
703 ; 354 assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
705 ; 356 if (((u8)CLK_Peripheral & (u8)0x10) == 0x00)
707 0096 9e ld a,xh
708 0097 a510 bcp a,#16
709 0099 2630 jrne L313
710 ; 358 if (CLK_NewState != DISABLE)
712 009b 7b02 ld a,(OFST+2,sp)
713 009d 2714 jreq L513
714 ; 361 CLK->PCKENR1 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
716 009f 7b01 ld a,(OFST+1,sp)
717 00a1 a40f and a,#15
718 00a3 5f clrw x
719 00a4 97 ld xl,a
720 00a5 a601 ld a,#1
721 00a7 5d tnzw x
722 00a8 2704 jreq L62
723 00aa L03:
724 00aa 48 sll a
725 00ab 5a decw x
726 00ac 26fc jrne L03
727 00ae L62:
728 00ae ca50c7 or a,20679
730 00b1 2013 jp LC002
731 00b3 L513:
732 ; 366 CLK->PCKENR1 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
734 00b3 7b01 ld a,(OFST+1,sp)
735 00b5 a40f and a,#15
736 00b7 5f clrw x
737 00b8 97 ld xl,a
738 00b9 a601 ld a,#1
739 00bb 5d tnzw x
740 00bc 2704 jreq L23
741 00be L43:
742 00be 48 sll a
743 00bf 5a decw x
744 00c0 26fc jrne L43
745 00c2 L23:
746 00c2 43 cpl a
747 00c3 c450c7 and a,20679
748 00c6 LC002:
749 00c6 c750c7 ld 20679,a
750 00c9 202e jra L123
751 00cb L313:
752 ; 371 if (CLK_NewState != DISABLE)
754 00cb 7b02 ld a,(OFST+2,sp)
755 00cd 2714 jreq L323
756 ; 374 CLK->PCKENR2 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
758 00cf 7b01 ld a,(OFST+1,sp)
759 00d1 a40f and a,#15
760 00d3 5f clrw x
761 00d4 97 ld xl,a
762 00d5 a601 ld a,#1
763 00d7 5d tnzw x
764 00d8 2704 jreq L63
765 00da L04:
766 00da 48 sll a
767 00db 5a decw x
768 00dc 26fc jrne L04
769 00de L63:
770 00de ca50ca or a,20682
772 00e1 2013 jp LC001
773 00e3 L323:
774 ; 379 CLK->PCKENR2 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
776 00e3 7b01 ld a,(OFST+1,sp)
777 00e5 a40f and a,#15
778 00e7 5f clrw x
779 00e8 97 ld xl,a
780 00e9 a601 ld a,#1
781 00eb 5d tnzw x
782 00ec 2704 jreq L24
783 00ee L44:
784 00ee 48 sll a
785 00ef 5a decw x
786 00f0 26fc jrne L44
787 00f2 L24:
788 00f2 43 cpl a
789 00f3 c450ca and a,20682
790 00f6 LC001:
791 00f6 c750ca ld 20682,a
792 00f9 L123:
793 ; 383 }
796 00f9 85 popw x
797 00fa 81 ret
985 ; 405 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState CLK_SwitchIT, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
985 ; 406 {
986 switch .text
987 00fb _CLK_ClockSwitchConfig:
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