📄 stm8s_itc.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
4 ; Optimizer V4.3.5 - 15 Feb 2011
47 ; 62 u8 ITC_GetCPUCC(void)
47 ; 63 {
49 switch .text
50 0000 _ITC_GetCPUCC:
54 ; 64 _asm("push cc");
57 0000 8a push cc
59 ; 65 _asm("pop a");
62 0001 84 pop a
64 ; 66 return; /* Ignore compiler warning, the returned value is in A register */
67 0002 81 ret
90 ; 97 void ITC_DeInit(void)
90 ; 98 {
91 switch .text
92 0003 _ITC_DeInit:
96 ; 99 ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
98 0003 35ff7f70 mov 32624,#255
99 ; 100 ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
101 0007 35ff7f71 mov 32625,#255
102 ; 101 ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
104 000b 35ff7f72 mov 32626,#255
105 ; 102 ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
107 000f 35ff7f73 mov 32627,#255
108 ; 103 ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
110 0013 35ff7f74 mov 32628,#255
111 ; 104 ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
113 0017 35ff7f75 mov 32629,#255
114 ; 105 ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
116 001b 35ff7f76 mov 32630,#255
117 ; 106 ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
119 001f 35ff7f77 mov 32631,#255
120 ; 107 }
123 0023 81 ret
148 ; 124 u8 ITC_GetSoftIntStatus(void)
148 ; 125 {
149 switch .text
150 0024 _ITC_GetSoftIntStatus:
154 ; 126 return (u8)(ITC_GetCPUCC() & CPU_CC_I1I0);
156 0024 adda call _ITC_GetCPUCC
158 0026 a428 and a,#40
161 0028 81 ret
438 .const: section .text
439 0000 L42:
440 0000 004a dc.w L14
441 0002 004a dc.w L14
442 0004 004a dc.w L14
443 0006 004a dc.w L14
444 0008 004f dc.w L34
445 000a 004f dc.w L34
446 000c 004f dc.w L34
447 000e 004f dc.w L34
448 0010 0054 dc.w L54
449 0012 0054 dc.w L54
450 0014 0054 dc.w L54
451 0016 0054 dc.w L54
452 0018 0059 dc.w L74
453 001a 0059 dc.w L74
454 001c 0059 dc.w L74
455 001e 0059 dc.w L74
456 0020 005e dc.w L15
457 0022 005e dc.w L15
458 0024 005e dc.w L15
459 0026 005e dc.w L15
460 0028 0063 dc.w L35
461 002a 0063 dc.w L35
462 002c 0063 dc.w L35
463 002e 0063 dc.w L35
464 0030 0068 dc.w L55
465 ; 144 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
465 ; 145 {
466 switch .text
467 0029 _ITC_GetSoftwarePriority:
469 0029 88 push a
470 002a 89 pushw x
471 00000002 OFST: set 2
474 ; 147 u8 Value = 0;
476 002b 0f02 clr (OFST+0,sp)
477 ; 151 assert_param(IS_ITC_IRQ_OK((u8)IrqNum));
479 ; 154 Mask = (u8)(0x03U << (((u8)IrqNum % 4U) * 2U));
481 002d a403 and a,#3
482 002f 48 sll a
483 0030 5f clrw x
484 0031 97 ld xl,a
485 0032 a603 ld a,#3
486 0034 5d tnzw x
487 0035 2704 jreq L61
488 0037 L02:
489 0037 48 sll a
490 0038 5a decw x
491 0039 26fc jrne L02
492 003b L61:
493 003b 6b01 ld (OFST-1,sp),a
494 ; 156 switch (IrqNum)
496 003d 7b03 ld a,(OFST+1,sp)
498 ; 197 default:
498 ; 198 break;
499 003f a119 cp a,#25
500 0041 242e jruge L312
501 0043 5f clrw x
502 0044 97 ld xl,a
503 0045 58 sllw x
504 0046 de0000 ldw x,(L42,x)
505 0049 fc jp (x)
506 004a L14:
507 ; 158 case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
507 ; 159 case ITC_IRQ_AWU:
507 ; 160 case ITC_IRQ_CLK:
507 ; 161 case ITC_IRQ_PORTA:
507 ; 162 Value = (u8)(ITC->ISPR1 & Mask); /* Read software priority */
509 004a c67f70 ld a,32624
510 ; 163 break;
512 004d 201c jp LC001
513 004f L34:
514 ; 164 case ITC_IRQ_PORTB:
514 ; 165 case ITC_IRQ_PORTC:
514 ; 166 case ITC_IRQ_PORTD:
514 ; 167 case ITC_IRQ_PORTE:
514 ; 168 Value = (u8)(ITC->ISPR2 & Mask); /* Read software priority */
516 004f c67f71 ld a,32625
517 ; 169 break;
519 0052 2017 jp LC001
520 0054 L54:
521 ; 170 case ITC_IRQ_CAN_RX:
521 ; 171 case ITC_IRQ_CAN_TX:
521 ; 172 case ITC_IRQ_SPI:
521 ; 173 case ITC_IRQ_TIM1_OVF:
521 ; 174 Value = (u8)(ITC->ISPR3 & Mask); /* Read software priority */
523 0054 c67f72 ld a,32626
524 ; 175 break;
526 0057 2012 jp LC001
527 0059 L74:
528 ; 176 case ITC_IRQ_TIM1_CAPCOM:
528 ; 177 case ITC_IRQ_TIM2_OVF:
528 ; 178 case ITC_IRQ_TIM2_CAPCOM:
528 ; 179 case ITC_IRQ_TIM3_OVF:
528 ; 180 Value = (u8)(ITC->ISPR4 & Mask); /* Read software priority */
530 0059 c67f73 ld a,32627
531 ; 181 break;
533 005c 200d jp LC001
534 005e L15:
535 ; 182 case ITC_IRQ_TIM3_CAPCOM:
535 ; 183 case ITC_IRQ_USART_TX:
535 ; 184 case ITC_IRQ_USART_RX:
535 ; 185 case ITC_IRQ_I2C:
535 ; 186 Value = (u8)(ITC->ISPR5 & Mask); /* Read software priority */
537 005e c67f74 ld a,32628
538 ; 187 break;
540 0061 2008 jp LC001
541 0063 L35:
542 ; 188 case ITC_IRQ_LINUART_TX:
542 ; 189 case ITC_IRQ_LINUART_RX:
542 ; 190 case ITC_IRQ_ADC:
542 ; 191 case ITC_IRQ_TIM4_OVF:
542 ; 192 Value = (u8)(ITC->ISPR6 & Mask); /* Read software priority */
544 0063 c67f75 ld a,32629
545 ; 193 break;
547 0066 2003 jp LC001
548 0068 L55:
549 ; 194 case ITC_IRQ_EEPROM_EEC:
549 ; 195 Value = (u8)(ITC->ISPR7 & Mask); /* Read software priority */
551 0068 c67f76 ld a,32630
552 006b LC001:
553 006b 1401 and a,(OFST-1,sp)
554 006d 6b02 ld (OFST+0,sp),a
555 ; 196 break;
557 ; 197 default:
557 ; 198 break;
559 006f 7b03 ld a,(OFST+1,sp)
560 0071 L312:
561 ; 201 Value >>= (u8)(((u8)IrqNum % 4u) * 2u);
563 0071 a403 and a,#3
564 0073 48 sll a
565 0074 5f clrw x
566 0075 97 ld xl,a
567 0076 7b02 ld a,(OFST+0,sp)
568 0078 5d tnzw x
569 0079 2704 jreq L62
570 007b L03:
571 007b 44 srl a
572 007c 5a decw x
573 007d 26fc jrne L03
574 007f L62:
575 ; 203 return((ITC_PriorityLevel_TypeDef)Value);
579 007f 5b03 addw sp,#3
580 0081 81 ret
644 switch .const
645 0032 L64:
646 0032 00b8 dc.w L512
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