📄 d3d8types.h
字号:
[19:16] type (dimensionality and data type)
[15:04] 0x0
[03:00] vertex register address (0..15)
Data Skip (no register load)
[31:29] 0x2
[28] 0x1
[27:20] 0x0
[19:16] count of DWORDS to skip over (0..15)
[15:00] 0x0
Vertex Input Memory from Tessellator Data (single DWORD token)
[31:29] 0x3
[28] indicates whether data is normals or u/v
[27:24] 0x0
[23:20] vertex register address (0..15)
[19:16] type (dimensionality)
[15:04] 0x0
[03:00] vertex register address (0..15)
Constant Memory from Shader (multiple DWORD token)
[31:29] 0x4
[28:25] count of 4*DWORD constants to load (0..15)
[24:07] 0x0
[06:00] constant memory address (0..95)
Extension Token (single or multiple DWORD token)
[31:29] 0x5
[28:24] count of additional DWORDs in token (0..31)
[23:00] extension-specific information
End-of-array token (single DWORD token)
[31:29] 0x7
[28:00] 0x1fffffff
The stream selector token must be immediately followed by a contiguous set of stream data definition tokens. This token sequence fully defines that stream, including the set of elements within the stream, the order in which the elements appear, the type of each element, and the vertex register into which to load an element.
Streams are allowed to include data which is not loaded into a vertex register, thus allowing data which is not used for this shader to exist in the vertex stream. This skipped data is defined only by a count of DWORDs to skip over, since the type information is irrelevant.
The token sequence:
Stream Select: stream=0
Stream Data Definition (Load): type=FLOAT3; register=3
Stream Data Definition (Load): type=FLOAT3; register=4
Stream Data Definition (Skip): count=2
Stream Data Definition (Load): type=FLOAT2; register=7
defines stream zero to consist of 4 elements, 3 of which are loaded into registers and the fourth skipped over. Register 3 is loaded with the first three DWORDs in each vertex interpreted as FLOAT data. Register 4 is loaded with the 4th, 5th, and 6th DWORDs interpreted as FLOAT data. The next two DWORDs (7th and 8th) are skipped over and not loaded into any vertex input register. Register 7 is loaded with the 9th and 10th DWORDS interpreted as FLOAT data.
Placing of tokens other than NOPs between the Stream Selector and Stream Data Definition tokens is disallowed.
*/
typedef enum _D3DVSD_TOKENTYPE
{
D3DVSD_TOKEN_NOP = 0, // NOP or extension
D3DVSD_TOKEN_STREAM, // stream selector
D3DVSD_TOKEN_STREAMDATA, // stream data definition (map to vertex input memory)
D3DVSD_TOKEN_TESSELLATOR, // vertex input memory from tessellator
D3DVSD_TOKEN_CONSTMEM, // constant memory from shader
D3DVSD_TOKEN_EXT, // extension
D3DVSD_TOKEN_END = 7, // end-of-array (requires all DWORD bits to be 1)
D3DVSD_FORCE_DWORD = 0x7fffffff,// force 32-bit size enum
} D3DVSD_TOKENTYPE;
#define D3DVSD_TOKENTYPESHIFT 29
#define D3DVSD_TOKENTYPEMASK (7 << D3DVSD_TOKENTYPESHIFT)
#define D3DVSD_STREAMNUMBERSHIFT 0
#define D3DVSD_STREAMNUMBERMASK (0xF << D3DVSD_STREAMNUMBERSHIFT)
#define D3DVSD_DATALOADTYPESHIFT 28
#define D3DVSD_DATALOADTYPEMASK (0x1 << D3DVSD_DATALOADTYPESHIFT)
#define D3DVSD_DATATYPESHIFT 16
#define D3DVSD_DATATYPEMASK (0xF << D3DVSD_DATATYPESHIFT)
#define D3DVSD_SKIPCOUNTSHIFT 16
#define D3DVSD_SKIPCOUNTMASK (0xF << D3DVSD_SKIPCOUNTSHIFT)
#define D3DVSD_VERTEXREGSHIFT 0
#define D3DVSD_VERTEXREGMASK (0x1F << D3DVSD_VERTEXREGSHIFT)
#define D3DVSD_VERTEXREGINSHIFT 20
#define D3DVSD_VERTEXREGINMASK (0xF << D3DVSD_VERTEXREGINSHIFT)
#define D3DVSD_CONSTCOUNTSHIFT 25
#define D3DVSD_CONSTCOUNTMASK (0xF << D3DVSD_CONSTCOUNTSHIFT)
#define D3DVSD_CONSTADDRESSSHIFT 0
#define D3DVSD_CONSTADDRESSMASK (0x7F << D3DVSD_CONSTADDRESSSHIFT)
#define D3DVSD_CONSTRSSHIFT 16
#define D3DVSD_CONSTRSMASK (0x1FFF << D3DVSD_CONSTRSSHIFT)
#define D3DVSD_EXTCOUNTSHIFT 24
#define D3DVSD_EXTCOUNTMASK (0x1F << D3DVSD_EXTCOUNTSHIFT)
#define D3DVSD_EXTINFOSHIFT 0
#define D3DVSD_EXTINFOMASK (0xFFFFFF << D3DVSD_EXTINFOSHIFT)
#define D3DVSD_MAKETOKENTYPE(tokenType) ((tokenType << D3DVSD_TOKENTYPESHIFT) & D3DVSD_TOKENTYPEMASK)
// macros for generation of CreateVertexShader Declaration token array
// Set current stream
// _StreamNumber [0..(MaxStreams-1)] stream to get data from
//
#define D3DVSD_STREAM( _StreamNumber ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_STREAM) | (_StreamNumber))
// Set tessellator stream
//
#define D3DVSD_STREAMTESSSHIFT 28
#define D3DVSD_STREAMTESSMASK (1 << D3DVSD_STREAMTESSSHIFT)
#define D3DVSD_STREAM_TESS( ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_STREAM) | (D3DVSD_STREAMTESSMASK))
// bind single vertex register to vertex element from vertex stream
//
// _VertexRegister [0..15] address of the vertex register
// _Type [D3DVSDT_*] dimensionality and arithmetic data type
#define D3DVSD_REG( _VertexRegister, _Type ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_STREAMDATA) | \
((_Type) << D3DVSD_DATATYPESHIFT) | (_VertexRegister))
// Skip _DWORDCount DWORDs in vertex
//
#define D3DVSD_SKIP( _DWORDCount ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_STREAMDATA) | 0x10000000 | \
((_DWORDCount) << D3DVSD_SKIPCOUNTSHIFT))
// load data into vertex shader constant memory
//
// _ConstantAddress [0..95] - address of constant array to begin filling data
// _Count [0..15] - number of constant vectors to load (4 DWORDs each)
// followed by 4*_Count DWORDS of data
//
#define D3DVSD_CONST( _ConstantAddress, _Count ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_CONSTMEM) | \
((_Count) << D3DVSD_CONSTCOUNTSHIFT) | (_ConstantAddress))
// enable tessellator generated normals
//
// _VertexRegisterIn [0..15] address of vertex register whose input stream
// will be used in normal computation
// _VertexRegisterOut [0..15] address of vertex register to output the normal to
//
#define D3DVSD_TESSNORMAL( _VertexRegisterIn, _VertexRegisterOut ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_TESSELLATOR) | \
((_VertexRegisterIn) << D3DVSD_VERTEXREGINSHIFT) | \
((0x02) << D3DVSD_DATATYPESHIFT) | (_VertexRegisterOut))
// enable tessellator generated surface parameters
//
// _VertexRegister [0..15] address of vertex register to output parameters
//
#define D3DVSD_TESSUV( _VertexRegister ) \
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_TESSELLATOR) | 0x10000000 | \
((0x01) << D3DVSD_DATATYPESHIFT) | (_VertexRegister))
// Generates END token
//
#define D3DVSD_END() 0xFFFFFFFF
// Generates NOP token
#define D3DVSD_NOP() 0x00000000
// bit declarations for _Type fields
#define D3DVSDT_FLOAT1 0x00 // 1D float expanded to (value, 0., 0., 1.)
#define D3DVSDT_FLOAT2 0x01 // 2D float expanded to (value, value, 0., 1.)
#define D3DVSDT_FLOAT3 0x02 // 3D float expanded to (value, value, value, 1.)
#define D3DVSDT_FLOAT4 0x03 // 4D float
#define D3DVSDT_D3DCOLOR 0x04 // 4D packed unsigned bytes mapped to 0. to 1. range
// Input is in D3DCOLOR format (ARGB) expanded to (R, G, B, A)
#define D3DVSDT_UBYTE4 0x05 // 4D unsigned byte
#define D3DVSDT_SHORT2 0x06 // 2D signed short expanded to (value, value, 0., 1.)
#define D3DVSDT_SHORT4 0x07 // 4D signed short
// assignments of vertex input registers for fixed function vertex shader
//
#define D3DVSDE_POSITION 0
#define D3DVSDE_BLENDWEIGHT 1
#define D3DVSDE_BLENDINDICES 2
#define D3DVSDE_NORMAL 3
#define D3DVSDE_PSIZE 4
#define D3DVSDE_DIFFUSE 5
#define D3DVSDE_SPECULAR 6
#define D3DVSDE_TEXCOORD0 7
#define D3DVSDE_TEXCOORD1 8
#define D3DVSDE_TEXCOORD2 9
#define D3DVSDE_TEXCOORD3 10
#define D3DVSDE_TEXCOORD4 11
#define D3DVSDE_TEXCOORD5 12
#define D3DVSDE_TEXCOORD6 13
#define D3DVSDE_TEXCOORD7 14
#define D3DVSDE_POSITION2 15
#define D3DVSDE_NORMAL2 16
// Maximum supported number of texture coordinate sets
#define D3DDP_MAXTEXCOORD 8
//
// Instruction Token Bit Definitions
//
#define D3DSI_OPCODE_MASK 0x0000FFFF
typedef enum _D3DSHADER_INSTRUCTION_OPCODE_TYPE
{
D3DSIO_NOP = 0, // PS/VS
D3DSIO_MOV , // PS/VS
D3DSIO_ADD , // PS/VS
D3DSIO_SUB , // PS
D3DSIO_MAD , // PS/VS
D3DSIO_MUL , // PS/VS
D3DSIO_RCP , // VS
D3DSIO_RSQ , // VS
D3DSIO_DP3 , // PS/VS
D3DSIO_DP4 , // PS/VS
D3DSIO_MIN , // VS
D3DSIO_MAX , // VS
D3DSIO_SLT , // VS
D3DSIO_SGE , // VS
D3DSIO_EXP , // VS
D3DSIO_LOG , // VS
D3DSIO_LIT , // VS
D3DSIO_DST , // VS
D3DSIO_LRP , // PS
D3DSIO_FRC , // VS
D3DSIO_M4x4 , // VS
D3DSIO_M4x3 , // VS
D3DSIO_M3x4 , // VS
D3DSIO_M3x3 , // VS
D3DSIO_M3x2 , // VS
D3DSIO_TEXCOORD = 64, // PS
D3DSIO_TEXKILL , // PS
D3DSIO_TEX , // PS
D3DSIO_TEXBEM , // PS
D3DSIO_TEXBEML , // PS
D3DSIO_TEXREG2AR , // PS
D3DSIO_TEXREG2GB , // PS
D3DSIO_TEXM3x2PAD , // PS
D3DSIO_TEXM3x2TEX , // PS
D3DSIO_TEXM3x3PAD , // PS
D3DSIO_TEXM3x3TEX , // PS
D3DSIO_TEXM3x3DIFF , // PS
D3DSIO_TEXM3x3SPEC , // PS
D3DSIO_TEXM3x3VSPEC , // PS
D3DSIO_EXPP , // VS
D3DSIO_LOGP , // VS
D3DSIO_CND , // PS
D3DSIO_DEF , // PS
D3DSIO_TEXREG2RGB , // PS
D3DSIO_TEXDP3TEX , // PS
D3DSIO_TEXM3x2DEPTH , // PS
D3DSIO_TEXDP3 , // PS
D3DSIO_TEXM3x3 , // PS
D3DSIO_TEXDEPTH , // PS
D3DSIO_CMP , // PS
D3DSIO_BEM , // PS
D3DSIO_PHASE = 0xFFFD,
D3DSIO_COMMENT = 0xFFFE,
D3DSIO_END = 0xFFFF,
D3DSIO_FORCE_DWORD = 0x7fffffff, // force 32-bit size enum
} D3DSHADER_INSTRUCTION_OPCODE_TYPE;
//
// Co-Issue Instruction Modifier - if set then this instruction is to be
// issued in parallel with the previous instruction(s) for which this bit
// is not set.
//
#define D3DSI_COISSUE 0x40000000
//
// Parameter Token Bit Definitions
//
#define D3DSP_REGNUM_MASK 0x00001FFF
// destination parameter write mask
#define D3DSP_WRITEMASK_0 0x00010000 // Component 0 (X;Red)
#define D3DSP_WRITEMASK_1 0x00020000 // Component 1 (Y;Green)
#define D3DSP_WRITEMASK_2 0x00040000 // Component 2 (Z;Blue)
#define D3DSP_WRITEMASK_3 0x00080000 // Component 3 (W;Alpha)
#define D3DSP_WRITEMASK_ALL 0x000F0000 // All Components
// destination parameter modifiers
#define D3DSP_DSTMOD_SHIFT 20
#define D3DSP_DSTMOD_MASK 0x00F00000
typedef enum _D3DSHADER_PARAM_DSTMOD_TYPE
{
D3DSPDM_NONE = 0<<D3DSP_DSTMOD_SHIFT, // nop
D3DSPDM_SATURATE= 1<<D3DSP_DSTMOD_SHIFT, // clamp to 0. to 1. range
D3DSPDM_FORCE_DWORD = 0x7fffffff, // force 32-bit size enum
} D3DSHADER_PARAM_DSTMOD_TYPE;
// destination parameter
#define D3DSP_DSTSHIFT_SHIFT 24
#define D3DSP_DSTSHIFT_MASK 0x0F000000
// destination/source parameter register type
#define D3DSP_REGTYPE_SHIFT 28
#define D3DSP_REGTYPE_MASK 0x70000000
typedef enum _D3DSHADER_PARAM_REGISTER_TYPE
{
D3DSPR_TEMP = 0<<D3DSP_REGTYPE_SHIFT, // Temporary Register File
D3DSPR_INPUT = 1<<D3DSP_REGTYPE_SHIFT, // Input Register File
D3DSPR_CONST = 2<<D3DSP_REGTYPE_SHIFT, // Constant Register File
D3DSPR_ADDR = 3<<D3DSP_REGTYPE_SHIFT, // Address Register (VS)
D3DSPR_TEXTURE = 3<<D3DSP_REGTYPE_SHIFT, // Texture Register File (PS)
D3DSPR_RASTOUT = 4<<D3DSP_REGTYPE_SHIFT, // Rasterizer Register File
D3DSPR_ATTROUT = 5<<D3DSP_REGTYPE_SHIFT, // Attribute Output Register File
D3DSPR_TEXCRDOUT= 6<<D3DSP_REGTYPE_SHIFT, // Texture Coordinate Output Register File
D3DSPR_FORCE_DWORD = 0x7fffffff, // force 32-bit size enum
} D3DSHADER_PARAM_REGISTER_TYPE;
// Register offsets in the Rasterizer Register File
//
typedef enum _D3DVS_RASTOUT_OFFSETS
{
D3DSRO_POSITION = 0,
D3DSRO_FOG,
D3DSRO_POINT_SIZE,
D3DSRO_FORCE_DWORD = 0x7fffffff, // force 32-bit size enum
} D3DVS_RASTOUT_OFFSETS;
// Source operand addressing modes
#define D3DVS_ADDRESSMODE_SHIFT 13
#define D3DVS_ADDRESSMODE_MASK (1 << D3DVS_ADDRESSMODE_SHIFT)
typedef enum _D3DVS_ADDRESSMODE_TYPE
{
D3DVS_ADDRMODE_ABSOLUTE = (0 << D3DVS_ADDRESSMODE_SHIFT),
D3DVS_ADDRMODE_RELATIVE = (1 << D3DVS_ADDRESSMODE_SHIFT), // Relative to register A0
D3DVS_ADDRMODE_FORCE_DWORD = 0x7fffffff, // force 32-bit size enum
} D3DVS_ADDRESSMODE_TYPE;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -