📄 dm9k8.c
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printk("RESET: TX Timeout %x\n", db->reset_tx_timeout);#endif return 0;}static void dm9K8_tx_done(unsigned long unused){ struct net_device *dev = dm9K8_dev; board_info_t *db = (board_info_t *)dev->priv; int nsr; DM9K8_DBUG(0, "dm9K8_tx_done()", 0); nsr = ior(db, DM9K8_NSR); if(nsr & 0x04) db->tx_pkt_cnt--; if(nsr & 0x08) db->tx_pkt_cnt--; if(nsr & 0x0c) netif_wake_queue(dev); return;}/* DM9K8 insterrupt handler receive the packet to upper layer, free the transmitted packet*/#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)static void dm9K8_interrupt(int irq, void *dev_id, struct pt_regs *regs)#elsestatic irqreturn_t dm9K8_interrupt(int irq, void *dev_id, struct pt_regs *regs)#endif{ struct net_device *dev = dev_id; board_info_t *db; int int_status; u8 reg_save; DM9K8_DBUG(0, "dm9K8_interrupt()", 0); /* A real interrupt coming */ db = (board_info_t *)dev->priv; spin_lock(&db->lock); /* Save previous register address */ reg_save = inb(db->io_addr); /* Disable all interrupt */ iow(db, DM9K8_IMR, DM9K8_DISINTR); /* Got DM9K8A/DM9010 interrupt status */ int_status = ior(db, DM9K8_ISR); /* Got ISR */ iow(db, DM9K8_ISR, int_status); /* Clear ISR status */ /* Link status change */ if (int_status & DM9K8_LINK_INTR) { if(ior(db,1)&0x40) /* link OK */ { /* Link partner not N-way able */ if ((!(phy_read(db,6)&0x01))&&((ior(db,1)&0xC0)==0x40)) { phy_write(db,0,0); db->nway=0; } } db->link_change =1; } /* Received the coming packet */ if (int_status & DM9K8_RX_INTR) dm9K8_packet_receive(dev); /* Trnasmit Interrupt check */ if (int_status & DM9K8_TX_INTR) tasklet_schedule(&dm9K8_tx_tasklet); /* Re-enable interrupt mask */ iow(db, DM9K8_IMR, DM9K8_REGFF); /* Restore previous register address */ outb(reg_save, db->io_addr); spin_unlock(&db->lock); return; #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) return IRQ_HANDLED;#endif}/* Get statistics from driver.*/static struct net_device_stats * dm9K8_get_stats(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; DM9K8_DBUG(0, "dm9K8_get_stats", 0); return &db->stats;}/* Process the upper socket ioctl command*/static int dm9K8_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd){ DM9K8_DBUG(0, "dm9K8_do_ioctl()", 0); return 0;}/* A periodic timer routine Dynamic media sense, allocated Rx buffer...*/static void dm9K8_timer(unsigned long data){ struct net_device *dev = (struct net_device *)data; board_info_t *db = (board_info_t *)dev->priv; u8 reg_save,reg1; u16 phy_reg6; DM9K8_DBUG(0, "dm9K8_timer()", 0); /* Save previous register address */ reg_save = inb(db->io_addr); /* TX timeout check */ if (dev->trans_start && ((jiffies-dev->trans_start)>DM9K8_TX_TIMEOUT)) { db->device_wait_reset = 1; db->reset_tx_timeout++; } if (db->link_change) { reg1 = ior(db,1); if(db->nway==0 &&(!(reg1&0x40))) { /* Enable AUTO-negotiation */ phy_write(db,4,0x61); phy_write(db,0,0x1200); } if((reg1=ior(db,1))&0x40) /* link OK */ { phy_reg6 = phy_read(db,6); /* Link partner not N-way able */ if ((!(phy_reg6&0x01))&&((reg1&0xC0)==0x40) && db->nway) { phy_write(db,0,0); db->nway=0; } if(db->nway==0 && (reg1&0x80)) { db->device_wait_reset=1; db->nway=1; } } db->link_change=0; } /* DM9008A dynamic RESET check and do */ if (db->device_wait_reset) { netif_stop_queue(dev); db->reset_counter++; db->device_wait_reset = 0; dev->trans_start = 0; dm9K8_init(dev); netif_wake_queue(dev); } /* Restore previous register address */ outb(reg_save, db->io_addr); /* Set timer again */ db->timer.expires = DM9K8_TIMER_WUT; add_timer(&db->timer);}#if !defined(CHECKSUM)#define check_rx_ready(a) ((a) == 0x01)#elseinline u8 check_rx_ready(u8 rxbyte){ if (!(rxbyte & 0x01)) return 0; return ((rxbyte >> 4) | 0x01);}#endif/* Received a packet and pass to upper layer*/static void dm9K8_packet_receive(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; struct sk_buff *skb; u8 rxbyte, val; u16 i, GoodPacket, tmplen = 0, MDRAH, MDRAL; rx_t rx; u16 * ptr = (u16*)℞ u8* rdptr; DM9K8_DBUG(0, "dm9K8_packet_receive()", 0); do { /*store the value of Memory Data Read address register*/ MDRAH=ior(db, DM9K8_MDRAH); MDRAL=ior(db, DM9K8_MDRAL); ior(db, DM9K8_MRCMDX); /* Dummy read */ rxbyte = inb(db->io_data); /* Got most updated data */ /* packet ready to receive check */ if(!(val = check_rx_ready(rxbyte))) break; /* A packet ready now & Get status/length */ GoodPacket = TRUE; outb(DM9K8_MRCMD, db->io_addr); /* Read packet status & length */ switch (db->io_mode) { case DM9K8_BYTE_MODE: *ptr = inb(db->io_data) + (inb(db->io_data) << 8); *(ptr+1) = inb(db->io_data) + (inb(db->io_data) << 8); break; case DM9K8_WORD_MODE: *ptr = inw(db->io_data); *(ptr+1) = inw(db->io_data); break; default: break; } /* Packet status check */ if (rx.desc.status & 0xbf) { GoodPacket = FALSE; if (rx.desc.status & 0x01) { db->stats.rx_fifo_errors++; //printk("<RX FIFO error>\n"); } if (rx.desc.status & 0x02) { db->stats.rx_crc_errors++; printk("<RX CRC error>\n"); } if (rx.desc.status & 0x80) { db->stats.rx_length_errors++; printk("<RX Length error>\n"); } if (rx.desc.status & 0x08) printk("<Physical Layer error>\n"); } if (!GoodPacket) { // drop this packet!!! switch (db->io_mode) { case DM9K8_BYTE_MODE: for (i=0; i<rx.desc.length; i++) inb(db->io_data); break; case DM9K8_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) inw(db->io_data); break; } continue;/*next the packet*/ } skb = dev_alloc_skb(rx.desc.length+4); if (skb == NULL ) { printk(KERN_INFO "%s: Memory squeeze.\n", dev->name); /*re-load the value into Memory data read address register*/ iow(db,DM9K8_MDRAH,MDRAH); iow(db,DM9K8_MDRAL,MDRAL); return; } else { /* Move data from DM9008A */ skb->dev = dev; skb_reserve(skb, 2); rdptr = (u8*)skb_put(skb, rx.desc.length - 4); /* Read received packet from RX SARM */ switch (db->io_mode) { case DM9K8_BYTE_MODE: for (i=0; i<rx.desc.length; i++) rdptr[i]=inb(db->io_data); break; case DM9K8_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) ((u16 *)rdptr)[i] = inw(db->io_data); break; } /* Pass to upper layer */ skb->protocol = eth_type_trans(skb,dev);#if defined(CHECKSUM) if (val == 0x01) skb->ip_summed = CHECKSUM_UNNECESSARY;#endif netif_rx(skb); db->stats.rx_packets++; db->stats.rx_bytes += rx.desc.length; } }while((rxbyte & 0x01) == DM9K8_PKT_RDY); }/* Read a word data from SROM*/static u16 read_srom_word(board_info_t *db, int offset){ iow(db, DM9K8_EPAR, offset); iow(db, DM9K8_EPCR, 0x4); udelay(200); iow(db, DM9K8_EPCR, 0x0); return (ior(db, DM9K8_EPDRL) + (ior(db, DM9K8_EPDRH) << 8) );}/* Set DM9008A multicast address*/static void dm9K8_hash_table(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; struct dev_mc_list *mcptr = dev->mc_list; int mc_cnt = dev->mc_count; u32 hash_val; u16 i, oft, hash_table[4]; DM9K8_DBUG(0, "dm9K8_hash_table()", 0); /* Set Node address */ for (i = 0, oft = 0x10; i < 6; i++, oft++) iow(db, oft, dev->dev_addr[i]); /* Clear Hash Table */ for (i = 0; i < 4; i++) hash_table[i] = 0x0; /* broadcast address */ hash_table[3] = 0x8000; /* the multicast address in Hash Table : 64 bits */ for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { hash_val = cal_CRC((char *)mcptr->dmi_addr, 6, 0) & 0x3f; hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); } /* Write the hash table to MAC MD table */ for (i = 0, oft = 0x16; i < 4; i++) { iow(db, oft++, hash_table[i] & 0xff); iow(db, oft++, (hash_table[i] >> 8) & 0xff); }}/* Calculate the CRC valude of the Rx packet flag = 1 : return the reverse CRC (for the received packet CRC) 0 : return the normal CRC (for Hash Table index)*/static unsigned long cal_CRC(unsigned char * Data, unsigned int Len, u8 flag){ u32 crc = ether_crc_le(Len, Data); if (flag) return ~crc; return crc; }/* Read a byte from I/O port*/static u8 ior(board_info_t *db, int reg){ outb(reg, db->io_addr); return inb(db->io_data);}/* Write a byte to I/O port*/static void iow(board_info_t *db, int reg, u8 value){ outb(reg, db->io_addr); outb(value, db->io_data);}/* Read a word from phyxcer*/static u16 phy_read(board_info_t *db, int reg){ /* Fill the phyxcer register into REG_0C */ iow(db, DM9K8_EPAR, DM9K8_PHY | reg); iow(db, DM9K8_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ iow(db, DM9K8_EPCR, 0x0); /* Clear phyxcer read command */ /* The read data keeps on REG_0D & REG_0E */ return ( ior(db, DM9K8_EPDRH) << 8 ) | ior(db, DM9K8_EPDRL); }/* Write a word to phyxcer*/static void phy_write(board_info_t *db, int reg, u16 value){ /* Fill the phyxcer register into REG_0C */ iow(db, DM9K8_EPAR, DM9K8_PHY | reg); /* Fill the written data into REG_0D & REG_0E */ iow(db, DM9K8_EPDRL, (value & 0xff)); iow(db, DM9K8_EPDRH, ( (value >> 8) & 0xff)); iow(db, DM9K8_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ iow(db, DM9K8_EPCR, 0x0); /* Clear phyxcer write command */}#ifdef MODULEMODULE_LICENSE("GPL");MODULE_AUTHOR("Bill, bill_wu@davicom.com.tw");MODULE_DESCRIPTION("Davicom DM9008A 10M ONLY Ethernet Driver");MODULE_PARM(mode, "i");MODULE_PARM(irq, "i");MODULE_PARM(iobase, "i");MODULE_PARM_DESC(mode,"Media Speed, 0:10MHD, 1:10MFD");MODULE_PARM_DESC(irq,"EtherLink IRQ number");MODULE_PARM_DESC(iobase, "EtherLink I/O base address");/* Description: when user used insmod to add module, system invoked init_module() to initilize and register.*/int init_module(void){ switch(mode) { case DM9K8_10MHD: /*case DM9K8_100MHD:*/ case DM9K8_10MFD: /*case DM9K8_100MFD:*/ media_mode = mode; break; default: media_mode = DM9K8_AUTO; } dm9K8_dev = dm9K8_probe1(); if(IS_ERR(dm9K8_dev)) return PTR_ERR(dm9K8_dev); return 0;}/* Description: when user used rmmod to delete module, system invoked clean_module() to un-register DEVICE.*/void cleanup_module(void){ struct net_device *dev = dm9K8_dev; DM9K8_DBUG(0, "clean_module()", 0); unregister_netdev(dm9K8_dev); release_region(dev->base_addr, 2);#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) kfree(dev);#else free_netdev(dev);#endif DM9K8_DBUG(0, "clean_module() exit", 0);}#endif
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