📄 bsp.lst
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257 break;
258
259 case 7:
260 IOCLR = 1 << 6;
\ ??LED_Off_7:
\ 00000080 1848 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 00000082 4021 MOVS R1,#+64
\ 00000084 0160 STR R1,[R0, #+0]
\ 00000086 2AE0 B ??LED_Off_17
261 break;
262
263 case 8:
264 IOCLR = 1 << 7;
\ ??LED_Off_8:
\ 00000088 1648 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 0000008A 8021 MOVS R1,#+128
\ 0000008C 0160 STR R1,[R0, #+0]
\ 0000008E 26E0 B ??LED_Off_17
265 break;
266
267 case 9:
268 IOCLR = 1 << 8;
\ ??LED_Off_9:
\ 00000090 1448 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 00000092 8021 MOVS R1,#+128
\ 00000094 4900 LSLS R1,R1,#+1 ;; #+256
\ 00000096 0160 STR R1,[R0, #+0]
\ 00000098 21E0 B ??LED_Off_17
269 break;
270
271 case 10:
272 IOCLR = 1 << 9;
\ ??LED_Off_10:
\ 0000009A 1248 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 0000009C 8021 MOVS R1,#+128
\ 0000009E 8900 LSLS R1,R1,#+2 ;; #+512
\ 000000A0 0160 STR R1,[R0, #+0]
\ 000000A2 1CE0 B ??LED_Off_17
273 break;
274
275 case 11:
276 IOCLR = 1 << 10;
\ ??LED_Off_11:
\ 000000A4 0F48 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000A6 8021 MOVS R1,#+128
\ 000000A8 C900 LSLS R1,R1,#+3 ;; #+1024
\ 000000AA 0160 STR R1,[R0, #+0]
\ 000000AC 17E0 B ??LED_Off_17
277 break;
278
279 case 12:
280 IOCLR = 1 << 11;
\ ??LED_Off_12:
\ 000000AE 0D48 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000B0 8021 MOVS R1,#+128
\ 000000B2 0901 LSLS R1,R1,#+4 ;; #+2048
\ 000000B4 0160 STR R1,[R0, #+0]
\ 000000B6 12E0 B ??LED_Off_17
281 break;
282
283 case 13:
284 IOCLR = 1 << 12;
\ ??LED_Off_13:
\ 000000B8 0A48 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000BA 8021 MOVS R1,#+128
\ 000000BC 4901 LSLS R1,R1,#+5 ;; #+4096
\ 000000BE 0160 STR R1,[R0, #+0]
\ 000000C0 0DE0 B ??LED_Off_17
285 break;
286
287 case 14:
288 IOCLR = 1 << 13;
\ ??LED_Off_14:
\ 000000C2 0848 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000C4 8021 MOVS R1,#+128
\ 000000C6 8901 LSLS R1,R1,#+6 ;; #+8192
\ 000000C8 0160 STR R1,[R0, #+0]
\ 000000CA 08E0 B ??LED_Off_17
289 break;
290
291 case 15:
292 IOCLR = 1 << 14;
\ ??LED_Off_15:
\ 000000CC 0548 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000CE 8021 MOVS R1,#+128
\ 000000D0 C901 LSLS R1,R1,#+7 ;; #+16384
\ 000000D2 0160 STR R1,[R0, #+0]
\ 000000D4 03E0 B ??LED_Off_17
293 break;
294
295 case 16:
296 IOCLR = 1 << 15;
\ ??LED_Off_16:
\ 000000D6 0348 LDR R0,??LED_Off_18 ;; 0xe002800c
\ 000000D8 8021 MOVS R1,#+128
\ 000000DA 0902 LSLS R1,R1,#+8 ;; #+32768
\ 000000DC 0160 STR R1,[R0, #+0]
297 break;
298 }
299 }
\ ??LED_Off_17:
\ 000000DE 01BC POP {R0}
\ 000000E0 0047 BX R0 ;; return
\ 000000E2 C046 Nop
\ ??LED_Off_18:
\ 000000E4 0C8002E0 DC32 0xe002800c
300
301 /*
302 *********************************************************************************************************
303 * TICKER INITIALIZATION
304 *
305 * Description : This function is called to initialize uC/OS-II's tick source (typically a timer generating
306 * interrupts every 1 to 100 mS).
307 *
308 * Arguments : none
309 *********************************************************************************************************
310 */
311
\ In segment CODE, align 4, keep-with-next
312 void Tmr_TickInit (void)
313 {
314 /* VIC TIMER #0 Initialization */
315 VICIntSelect &= ~(1 << VIC_TIMER0); /* Enable interrupts */
\ Tmr_TickInit:
\ 00000000 1248 LDR R0,??Tmr_TickInit_0 ;; 0xfffff00c
\ 00000002 1249 LDR R1,??Tmr_TickInit_0 ;; 0xfffff00c
\ 00000004 0968 LDR R1,[R1, #+0]
\ 00000006 1022 MOVS R2,#+16
\ 00000008 9143 BICS R1,R1,R2
\ 0000000A 0160 STR R1,[R0, #+0]
316 VICVectAddr2 = (INT32U)Tmr_TickISR_Handler; /* Set the vector address */
\ 0000000C .... LDR R0,??DataTable7 ;; 0xfffff108
\ 0000000E 1049 LDR R1,??Tmr_TickInit_0+0x4 ;; Tmr_TickISR_Handler
\ 00000010 0160 STR R1,[R0, #+0]
317 VICVectCntl2 = 0x20 | VIC_TIMER0; /* Enable vectored interrupts */
\ 00000012 1048 LDR R0,??Tmr_TickInit_0+0x8 ;; 0xfffff208
\ 00000014 2421 MOVS R1,#+36
\ 00000016 0160 STR R1,[R0, #+0]
318 VICIntEnable = (1 << VIC_TIMER0); /* Enable Interrupts */
\ 00000018 0F48 LDR R0,??Tmr_TickInit_0+0xC ;; 0xfffff010
\ 0000001A 1021 MOVS R1,#+16
\ 0000001C 0160 STR R1,[R0, #+0]
319
320 T0TCR = 0; /* Disable timer 0. */
\ 0000001E 0F48 LDR R0,??Tmr_TickInit_0+0x10 ;; 0xe0004004
\ 00000020 0021 MOVS R1,#+0
\ 00000022 0160 STR R1,[R0, #+0]
321 T0PC = 0; /* Prescaler is set to no division. */
\ 00000024 0E48 LDR R0,??Tmr_TickInit_0+0x14 ;; 0xe0004010
\ 00000026 0021 MOVS R1,#+0
\ 00000028 0160 STR R1,[R0, #+0]
322 T0MR0 = CPU_PERIPHERAL_CLK_FREQ / OS_TICKS_PER_SEC; /* Count up to this value. */
\ 0000002A 0E48 LDR R0,??Tmr_TickInit_0+0x18 ;; 0xe0004018
\ 0000002C 9021 MOVS R1,#+144
\ 0000002E 0902 LSLS R1,R1,#+8 ;; #+36864
\ 00000030 0160 STR R1,[R0, #+0]
323 T0MCR = 3; /* Reset and interrupt on MR0 (match register 0). */
\ 00000032 0D48 LDR R0,??Tmr_TickInit_0+0x1C ;; 0xe0004014
\ 00000034 0321 MOVS R1,#+3
\ 00000036 0160 STR R1,[R0, #+0]
324 T0CCR = 0; /* Capture is disabled. */
\ 00000038 0C48 LDR R0,??Tmr_TickInit_0+0x20 ;; 0xe0004028
\ 0000003A 0021 MOVS R1,#+0
\ 0000003C 0160 STR R1,[R0, #+0]
325 T0EMR = 0; /* No external match output. */
\ 0000003E 0C48 LDR R0,??Tmr_TickInit_0+0x24 ;; 0xe000403c
\ 00000040 0021 MOVS R1,#+0
\ 00000042 0160 STR R1,[R0, #+0]
326 T0TCR = 1; /* Enable timer 0 */
\ 00000044 0548 LDR R0,??Tmr_TickInit_0+0x10 ;; 0xe0004004
\ 00000046 0121 MOVS R1,#+1
\ 00000048 0160 STR R1,[R0, #+0]
327 }
\ 0000004A 7047 BX LR ;; return
\ ??Tmr_TickInit_0:
\ 0000004C 0CF0FFFF DC32 0xfffff00c
\ 00000050 ........ DC32 Tmr_TickISR_Handler
\ 00000054 08F2FFFF DC32 0xfffff208
\ 00000058 10F0FFFF DC32 0xfffff010
\ 0000005C 044000E0 DC32 0xe0004004
\ 00000060 104000E0 DC32 0xe0004010
\ 00000064 184000E0 DC32 0xe0004018
\ 00000068 144000E0 DC32 0xe0004014
\ 0000006C 284000E0 DC32 0xe0004028
\ 00000070 3C4000E0 DC32 0xe000403c
328
329
330 /*
331 *********************************************************************************************************
332 * IRQ ISR HANDLER
333 *
334 * Description : This function is called by OS_CPU_IRQ_ISR() to determine the source of the interrupt
335 * and process it accordingly.
336 *
337 * Arguments : none
338 *********************************************************************************************************
339 */
340
\ In segment CODE, align 4, keep-with-next
341 void OS_CPU_IRQ_ISR_Handler (void)
342 {
\ OS_CPU_IRQ_ISR_Handler:
\ 00000000 00B5 PUSH {LR}
343 PFNCT pfnct;
344
345
346 #if 1
347 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
\ 00000002 .... LDR R0,??DataTable6 ;; 0xfffff030
\ 00000004 0068 LDR R0,[R0, #+0]
348 if (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
\ 00000006 0100 MOVS R1,R0
\ 00000008 0029 CMP R1,#+0
\ 0000000A 01D0 BEQ ??OS_CPU_IRQ_ISR_Handler_0
349 (*pfnct)(); /* Execute the ISR for the interrupting device */
\ 0000000C ........ BL ??rT_BX_R0
350 }
351 #else
352 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
353 while (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
354 (*pfnct)(); /* Execute the ISR for the interrupting device */
355 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
356 }
357 #endif
358 }
\ ??OS_CPU_IRQ_ISR_Handler_0:
\ 00000010 01BC POP {R0}
\ 00000012 0047 BX R0 ;; return
359
360
361 /*
362 *********************************************************************************************************
363 * FIQ ISR HANDLER
364 *
365 * Description : This function is called by OS_CPU_FIQ_ISR() to determine the source of the interrupt
366 * and process it accordingly.
367 *
368 * Arguments : none
369 *********************************************************************************************************
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