📄 bsp.s79
字号:
DC32 0xfffff010
DC32 0xe0004004
DC32 0xe0004010
DC32 0xe0004018
DC32 0xe0004014
DC32 0xe0004028
DC32 0xe000403c
CFI EndBlock cfiBlock9
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock10 Using cfiCommon0
CFI NoFunction
ARM
??OS_CPU_IRQ_ISR_Handler??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock10
REQUIRE OS_CPU_IRQ_ISR_Handler
// 328
// 329
// 330 /*
// 331 *********************************************************************************************************
// 332 * IRQ ISR HANDLER
// 333 *
// 334 * Description : This function is called by OS_CPU_IRQ_ISR() to determine the source of the interrupt
// 335 * and process it accordingly.
// 336 *
// 337 * Arguments : none
// 338 *********************************************************************************************************
// 339 */
// 340
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock11 Using cfiCommon1
CFI Function OS_CPU_IRQ_ISR_Handler
THUMB
// 341 void OS_CPU_IRQ_ISR_Handler (void)
// 342 {
OS_CPU_IRQ_ISR_Handler:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
// 343 PFNCT pfnct;
// 344
// 345
// 346 #if 1
// 347 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
LDR R0,??DataTable6 ;; 0xfffff030
LDR R0,[R0, #+0]
// 348 if (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
MOVS R1,R0
BEQ ??OS_CPU_IRQ_ISR_Handler_0
// 349 (*pfnct)(); /* Execute the ISR for the interrupting device */
BL ??rT_BX_R0
// 350 }
// 351 #else
// 352 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
// 353 while (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
// 354 (*pfnct)(); /* Execute the ISR for the interrupting device */
// 355 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
// 356 }
// 357 #endif
// 358 }
??OS_CPU_IRQ_ISR_Handler_0:
POP {R0}
BX R0 ;; return
CFI EndBlock cfiBlock11
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock12 Using cfiCommon0
CFI NoFunction
ARM
??OS_CPU_FIQ_ISR_Handler??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock12
REQUIRE OS_CPU_FIQ_ISR_Handler
// 359
// 360
// 361 /*
// 362 *********************************************************************************************************
// 363 * FIQ ISR HANDLER
// 364 *
// 365 * Description : This function is called by OS_CPU_FIQ_ISR() to determine the source of the interrupt
// 366 * and process it accordingly.
// 367 *
// 368 * Arguments : none
// 369 *********************************************************************************************************
// 370 */
// 371
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock13 Using cfiCommon1
CFI Function OS_CPU_FIQ_ISR_Handler
THUMB
// 372 void OS_CPU_FIQ_ISR_Handler (void)
// 373 {
OS_CPU_FIQ_ISR_Handler:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
// 374 PFNCT pfnct;
// 375
// 376
// 377 #if 1
// 378 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
LDR R0,??DataTable6 ;; 0xfffff030
LDR R0,[R0, #+0]
// 379 if (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
MOVS R1,R0
BEQ ??OS_CPU_FIQ_ISR_Handler_0
// 380 (*pfnct)(); /* Execute the ISR for the interrupting device */
BL ??rT_BX_R0
// 381 }
// 382 #else
// 383 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
// 384 while (pfnct != (PFNCT)0) { /* Make sure we don't have a NULL pointer */
// 385 (*pfnct)(); /* Execute the ISR for the interrupting device */
// 386 pfnct = (PFNCT)VICVectAddr; /* Read the interrupt vector from the VIC */
// 387 }
// 388 #endif
// 389 }
??OS_CPU_FIQ_ISR_Handler_0:
POP {R0}
BX R0 ;; return
CFI EndBlock cfiBlock13
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock14 Using cfiCommon0
CFI NoFunction
ARM
??Tmr_TickISR_Handler??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock14
REQUIRE Tmr_TickISR_Handler
// 390
// 391
// 392 /*
// 393 *********************************************************************************************************
// 394 * TIMER #0 IRQ HANDLER
// 395 *
// 396 * Description : This function handles the timer interrupt that is used to generate TICKs for uC/OS-II.
// 397 *
// 398 * Arguments : none
// 399 *********************************************************************************************************
// 400 */
// 401
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock15 Using cfiCommon1
CFI Function Tmr_TickISR_Handler
THUMB
// 402 void Tmr_TickISR_Handler (void)
// 403 {
Tmr_TickISR_Handler:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
// 404 T0IR = 0xFF; /* Clear timer #0 interrupt */
LDR R0,??Tmr_TickISR_Handler_0 ;; 0xe0004000
MOVS R1,#+255
STR R1,[R0, #+0]
// 405 OSTimeTick(); /* If the interrupt is from the tick source, call OSTimeTick() */
_BLF OSTimeTick,??OSTimeTick??rT
// 406 VICVectAddr = 0;
LDR R0,??DataTable6 ;; 0xfffff030
MOVS R1,#+0
STR R1,[R0, #+0]
// 407 }
POP {R0}
BX R0 ;; return
Nop
DATA
??Tmr_TickISR_Handler_0:
DC32 0xe0004000
CFI EndBlock cfiBlock15
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable6:
DC32 0xfffff030
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock16 Using cfiCommon0
CFI NoFunction
ARM
??VIC_Init??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock16
REQUIRE VIC_Init
// 408
// 409
// 410 /*
// 411 *********************************************************************************************************
// 412 * Vectored Interrupt Controller
// 413 *********************************************************************************************************
// 414 */
// 415
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock17 Using cfiCommon1
CFI Function VIC_Init
THUMB
// 416 void VIC_Init (void)
// 417 {
// 418 VICIntEnClear = 0xFFFFFFFF; /* Disable ALL interrupts */
VIC_Init:
LDR R0,??VIC_Init_0 ;; 0xfffff014
MOVS R1,#+0
MVNS R1,R1 ;; #-1
STR R1,[R0, #+0]
// 419 VICProtection = 0; /* Setup interrupt controller */
LDR R0,??VIC_Init_0+0x4 ;; 0xfffff020
MOVS R1,#+0
STR R1,[R0, #+0]
// 420
// 421 VICVectAddr1 = (INT32U)VIC_DummyWDT; /* Set the vector address */
LDR R0,??VIC_Init_0+0x8 ;; 0xfffff104
LDR R1,??VIC_Init_0+0xC ;; VIC_DummyWDT
STR R1,[R0, #+0]
// 422 VICVectAddr2 = (INT32U)VIC_DummyTIMER0;
LDR R0,??DataTable7 ;; 0xfffff108
LDR R1,??VIC_Init_0+0x10 ;; VIC_DummyTIMER0
STR R1,[R0, #+0]
// 423 VICVectAddr3 = (INT32U)VIC_DummyTIMER1;
LDR R0,??VIC_Init_0+0x14 ;; 0xfffff10c
LDR R1,??VIC_Init_0+0x18 ;; VIC_DummyTIMER1
STR R1,[R0, #+0]
// 424 VICVectAddr4 = (INT32U)VIC_DummyUART0;
LDR R0,??VIC_Init_0+0x1C ;; 0xfffff110
LDR R1,??VIC_Init_0+0x20 ;; VIC_DummyUART0
STR R1,[R0, #+0]
// 425 VICVectAddr5 = (INT32U)VIC_DummyUART1;
LDR R0,??VIC_Init_0+0x24 ;; 0xfffff114
LDR R1,??VIC_Init_0+0x28 ;; VIC_DummyUART1
STR R1,[R0, #+0]
// 426 VICVectAddr6 = (INT32U)VIC_DummyPWM0;
LDR R0,??VIC_Init_0+0x2C ;; 0xfffff118
LDR R1,??VIC_Init_0+0x30 ;; VIC_DummyPWM0
STR R1,[R0, #+0]
// 427 VICVectAddr7 = (INT32U)VIC_DummyI2C;
LDR R0,??VIC_Init_0+0x34 ;; 0xfffff11c
LDR R1,??VIC_Init_0+0x38 ;; VIC_DummyI2C
STR R1,[R0, #+0]
// 428 VICVectAddr8 = (INT32U)VIC_DummySPI;
LDR R0,??VIC_Init_0+0x3C ;; 0xfffff120
LDR R1,??VIC_Init_0+0x40 ;; VIC_DummySPI
STR R1,[R0, #+0]
// 429 VICVectAddr9 = (INT32U)VIC_DummyRTC;
LDR R0,??VIC_Init_0+0x44 ;; 0xfffff124
LDR R1,??VIC_Init_0+0x48 ;; VIC_DummyRTC
STR R1,[R0, #+0]
// 430 VICVectAddr10 = (INT32U)VIC_DummyEINT0;
LDR R0,??VIC_Init_0+0x4C ;; 0xfffff128
LDR R1,??VIC_Init_0+0x50 ;; VIC_DummyEINT0
STR R1,[R0, #+0]
// 431 VICVectAddr11 = (INT32U)VIC_DummyEINT1;
LDR R0,??VIC_Init_0+0x54 ;; 0xfffff12c
LDR R1,??VIC_Init_0+0x58 ;; VIC_DummyEINT1
STR R1,[R0, #+0]
// 432 VICVectAddr12 = (INT32U)VIC_DummyEINT2;
LDR R0,??VIC_Init_0+0x5C ;; 0xfffff130
LDR R1,??VIC_Init_0+0x60 ;; VIC_DummyEINT2
STR R1,[R0, #+0]
// 433 }
BX LR ;; return
DATA
??VIC_Init_0:
DC32 0xfffff014
DC32 0xfffff020
DC32 0xfffff104
DC32 VIC_DummyWDT
DC32 VIC_DummyTIMER0
DC32 0xfffff10c
DC32 VIC_DummyTIMER1
DC32 0xfffff110
DC32 VIC_DummyUART0
DC32 0xfffff114
DC32 VIC_DummyUART1
DC32 0xfffff118
DC32 VIC_DummyPWM0
DC32 0xfffff11c
DC32 VIC_DummyI2C
DC32 0xfffff120
DC32 VIC_DummySPI
DC32 0xfffff124
DC32 VIC_DummyRTC
DC32 0xfffff128
DC32 VIC_DummyEINT0
DC32 0xfffff12c
DC32 VIC_DummyEINT1
DC32 0xfffff130
DC32 VIC_DummyEINT2
CFI EndBlock cfiBlock17
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable7:
DC32 0xfffff108
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock18 Using cfiCommon0
CFI NoFunction
ARM
??VIC_Dummy??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock18
REQUIRE VIC_Dummy
// 434
// 435
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock19 Using cfiCommon1
CFI Function VIC_Dummy
THUMB
// 436 void VIC_Dummy (void)
// 437 {
VIC_Dummy:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
// 438 while (1) {
// 439 (void)VIC_SpuriousInt;
??VIC_Dummy_0:
B ??VIC_Dummy_0
CFI EndBlock cfiBlock19
// 440 }
// 441 }
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock20 Using cfiCommon0
CFI NoFunction
ARM
??VIC_DummyWDT??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock20
REQUIRE VIC_DummyWDT
// 442
// 443
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock21 Using cfiCommon1
CFI Function VIC_DummyWDT
THUMB
// 444 void VIC_DummyWDT (void)
// 445 {
VIC_DummyWDT:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
// 446 VIC_SpuriousInt = VIC_WDT;
LDR R0,??DataTable19 ;; VIC_SpuriousInt
MOVS R1,#+0
STR R1,[R0, #+0]
// 447 VIC_Dummy();
BL VIC_Dummy
// 448 }
POP {R0}
BX R0 ;; return
CFI EndBlock cfiBlock21
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock22 Using cfiCommon0
CFI NoFunction
ARM
??VIC_DummyTIMER0??rA:
ADD R12,PC,#+1
BX R12
CFI EndBlock cfiBlock22
REQUIRE VIC_DummyTIMER0
// 449
// 450
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock23 Using cfiCommon1
CFI Function VIC_DummyTIMER0
THUMB
// 451 void VIC_DummyTIMER0 (void)
// 452 {
VIC_DummyTIMER0:
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
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