class.ptf

参加今年的比赛肯定要用的。谢谢支持。祝大家好运！

CLASS user_logic_SEG7_LUT_8
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "mk_user_logic_SEG7_LUT_8.pl";
   }
   MODULE_DEFAULTS 
   {
      class = "user_logic_SEG7_LUT_8";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      SLAVE avalonS
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "native";
            Address_Width = "0";
            Data_Width = "32";
            Has_IRQ = "0";
            Has_Base_Address = "1";
            Read_Wait_States = "0ns";
            Write_Wait_States = "0ns";
            Setup_Time = "0ns";
            Hold_Time = "0ns";
            Is_Memory_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT oSEG0
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG1
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG2
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG3
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG4
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG5
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG6
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT oSEG7
            {
               width = "7";
               direction = "output";
               type = "export";
            }
            PORT iDIG
            {
               width = "32";
               direction = "input";
               type = "writedata";
            }
            PORT iWR
            {
               width = "1";
               direction = "input";
               type = "write";
            }
            PORT iCLK
            {
               width = "1";
               direction = "input";
               type = "clk";
            }
            PORT iRST_N
            {
               width = "1";
               direction = "input";
               type = "reset_n";
            }
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "oSEG0";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "oSEG1";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "oSEG2";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "oSEG3";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "oSEG4";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "oSEG5";
               radix = "hexadecimal";
            }
            SIGNAL g
            {
               name = "oSEG6";
               radix = "hexadecimal";
            }
            SIGNAL h
            {
               name = "oSEG7";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "iDIG";
               radix = "hexadecimal";
            }
            SIGNAL j
            {
               name = "iWR";
            }
            SIGNAL k
            {
               name = "iCLK";
            }
            SIGNAL l
            {
               name = "iRST_N";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "SEG7_LUT_8";
         technology = "User Logic";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "SEG7_LUT_8";
      black_box = "0";
      vhdl_synthesis_files = "";
      verilog_synthesis_files = "SEG7_LUT.v,SEG7_LUT_8.v";
      black_box_files = "";
   }
}