sixnet.c

linux下的BOOT程序原码,有需要的可以来下,保证好用

	    rtc_get(&tmp);	/* get time from DS1306 RTC */

	    /* convert to seconds since 1970 */
	    tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
			 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);

	    immap->im_sitk.sitk_rtck = KAPWR_KEY;
	    immap->im_sit.sit_rtc = tim;
	}

	/* set up ethernet address for SCC ethernet. If eth1addr
	 * is present it gets a unique address, otherwise it
	 * shares the FEC address.
	 */
	s = getenv("eth1addr");
	if (s == NULL)
		s = getenv("ethaddr");
	for (reg=0; reg<6; ++reg) {
		bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
		if (s)
			s = (*e) ? e+1 : e;
	}

	return (0);
}

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
void nand_init(void)
{
	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);

	printf ("%4lu MB\n", totlen >> 20);
}
#endif

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'.
 *
 * The memory size MUST be a power of 2 for this to work.
 *
 * The only memory modified is 8 bytes at offset 0. This is important
 * since for the SRAM this location is reserved for autosizing, so if
 * it is modified and the board is reset before ram_size() completes
 * no damage is  done. Normally even the memory at 0 is preserved. The
 * higher SRAM addresses may contain battery backed RAM disk data which
 * must never be corrupted.
 */

static long ram_size(ulong *base, long maxsize)
{
    volatile long	*test_addr;
    volatile ulong	*base_addr = base;
    ulong		ofs;		/* byte offset from base_addr */
    ulong		save;		/* to make test non-destructive */
    ulong		save2;		/* to make test non-destructive */
    long		ramsize = -1;	/* size not determined yet */

    save = *base_addr;		/* save value at 0 so can restore */
    save2 = *(base_addr+1);	/* save value at 4 so can restore */

    /* is any SRAM present? */
    *base_addr = 0x5555aaaa;

    /* It is important to drive the data bus with different data so
     * it doesn't remember the value and look like RAM that isn't there.
     */
    *(base_addr + 1) = 0xaaaa5555;	/* use write to modify data bus */

    if (*base_addr != 0x5555aaaa)
	ramsize = 0;		/* no RAM present, or defective */
    else {
	*base_addr = 0xaaaa5555;
	*(base_addr + 1) = 0x5555aaaa;	/* use write to modify data bus */
	if (*base_addr != 0xaaaa5555)
	    ramsize = 0;	/* no RAM present, or defective */
    }

    /* now size it if any is present */
    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
	test_addr = (long*)((long)base_addr + ofs);	/* location to test */

	*base_addr = ~*test_addr;
	if (*base_addr == *test_addr)
	    ramsize = ofs;	/* wrapped back to 0, so this is the size */
    }

    *base_addr = save;		/* restore value at 0 */
    *(base_addr+1) = save2;	/* restore value at 4 */
    return (ramsize);
}

/* ------------------------------------------------------------------------- */
/* sdram table based on the FADS manual                                      */
/* for chip MB811171622A-100                                                 */

/* this table is for 50MHz operation, it should work at all lower speeds */

const uint sdram_table[] =
{
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* precharge and Mode Register Set initialization (offset 5).
	 * This is also entered at offset 6 to do Mode Register Set
	 * without the precharge.
	 */
	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	/* FADS had 0x1f27fc04, ...
	 * but most other boards have 0x1f07fc04, which
	 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
	 * like the single read.
	 * This seems better so I am going with the change.
	 */
	0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_ };

/* ------------------------------------------------------------------------- */

#define	SDRAM_MAX_SIZE		0x10000000	/* max 256 MB SDRAM */

/* precharge and set Mode Register */
#define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
			  MCR_MB_CS3 |			/* chip select    */ \
			  MCR_MLCF(1) | MCR_MAD(5))	/* 1 time at 0x05 */

/* set Mode Register, no precharge */
#define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
			  MCR_MB_CS3 |			/* chip select    */ \
			  MCR_MLCF(1) | MCR_MAD(6))	/* 1 time at 0x06 */

/* runs refresh loop twice so get 8 refresh cycles */
#define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
			  MCR_MB_CS3 |			/* chip select    */ \
			  MCR_MLCF(2) | MCR_MAD(0x30))	/* twice at 0x30  */

/* MAMR values work in either mamr or mbmr */
#define SDRAM_MAMR_BASE  /* refresh at 50MHz */				  \
			 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE		  \
			 | MAMR_DSA_1_CYCL	/* 1 cycle disable */	  \
			 | MAMR_RLFA_1X		/* Read loop 1 time */	  \
			 | MAMR_WLFA_1X		/* Write loop 1 time */	  \
			 | MAMR_TLFA_4X)	/* Timer loop 4 times */
/* 8 column SDRAM */
#define SDRAM_MAMR_8COL	(SDRAM_MAMR_BASE				  \
			 | MAMR_AMA_TYPE_0	/* Address MUX 0 */	  \
			 | MAMR_G0CLA_A11)	/* GPL0 A11[MPC] */

/* 9 column SDRAM */
#define SDRAM_MAMR_9COL	(SDRAM_MAMR_BASE				  \
			 | MAMR_AMA_TYPE_1	/* Address MUX 1 */	  \
			 | MAMR_G0CLA_A10)	/* GPL0 A10[MPC] */

/* base address 0, 32-bit port, SDRAM UPM, valid */
#define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)

/*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
#define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)

/* This is the Mode Select Register value for the SDRAM.
 * Burst length: 4
 * Burst Type: sequential
 * CAS Latency: 2
 * Write Burst Length: burst
 */
#define SDRAM_MODE   0x22	/* CAS latency 2, burst length 4 */

/* ------------------------------------------------------------------------- */

long int initdram(int board_type)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	uint size_sdram = 0;
	uint size_sdram9 = 0;
	uint base = 0;		/* SDRAM must start at 0 */
	int i;

	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

	/* Configure the refresh (mostly).  This needs to be
	 * based upon processor clock speed and optimized to provide
	 * the highest level of performance.
	 *
	 * Preliminary prescaler for refresh.
	 * This value is selected for four cycles in 31.2 us,
	 * which gives 8192 cycles in 64 milliseconds.
	 * This may be too fast, but works for any memory.
	 * It is adjusted to 4096 cycles in 64 milliseconds if
	 * possible once we know what memory we have.
	 *
	 * We have to be careful changing UPM registers after we
	 * ask it to run these commands.
	 *
	 * PTA - periodic timer period for our design is
	 *       50 MHz x 31.2us
	 *       ---------------  = 195
	 *       1 x 8 x 1
	 *
	 *    50MHz clock
	 *    31.2us refresh interval
	 *    SCCR[DFBRG] 0
	 *    PTP divide by 8
	 *    1 chip select
	 */
	memctl->memc_mptpr = MPTPR_PTP_DIV8;	/* 0x0800 */
	memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */

	/* The SDRAM Mode Register value is shifted left 2 bits since
	 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
	 */
	memctl->memc_mar = SDRAM_MODE << 2;	/* MRS code */
	udelay(200);		/* SDRAM needs 200uS before set it up */

	/* Now run the precharge/nop/mrs commands. */
	memctl->memc_mcr = SDRAM_MCR_PRE;
	udelay(2);

	/* Run 8 refresh cycles (2 sets of 4) */
	memctl->memc_mcr = SDRAM_MCR_REFR;	/* run refresh twice */
	udelay(2);

	/* some brands want Mode Register set after the refresh
	 * cycles. This shouldn't hurt anything for the brands
	 * that were happy with the first time we set it.
	 */
	memctl->memc_mcr = SDRAM_MCR_MRS;
	udelay(2);

	memctl->memc_mamr = SDRAM_MAMR_8COL;	/* enable refresh */
	memctl->memc_or3 = SDRAM_OR_PRELIM;
	memctl->memc_br3 = SDRAM_BR_VALUE + base;

	/* Some brands need at least 10 DRAM accesses to stabilize.
	 * It wont hurt the brands that don't.
	 */
	for (i=0; i<10; ++i) {
		volatile ulong *addr = (volatile ulong *)base;
		ulong val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/* Check SDRAM memory Size in 8 column mode.
	 * For a 9 column memory we will get half the actual size.
	 */
	size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);

	/* Check SDRAM memory Size in 9 column mode.
	 * For an 8 column memory we will see at most 4 megabytes.
	 */
	memctl->memc_mamr = SDRAM_MAMR_9COL;
	size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);

	if (size_sdram < size_sdram9)	/* leave configuration at 9 columns */
		size_sdram = size_sdram9;
	else				/* go back to 8 columns */
		memctl->memc_mamr = SDRAM_MAMR_8COL;

	/* adjust or3 for actual size of SDRAM
	 */
	memctl->memc_or3 |= ORMASK(size_sdram);

	/* Adjust refresh rate depending on SDRAM type.
	 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
	 * it at the current (fast) rate.
	 * For 16, 64 and 128 MBit half the rate will do.
	 */
	if (size_sdram <= 32 * 1024 * 1024)
		memctl->memc_mptpr = MPTPR_PTP_DIV16;	/* 0x0400 */

	return (size_sdram);
}