sixnet.c

linux下的BOOT程序原码,有需要的可以来下,保证好用

/*
 * (C) Copyright 2001, 2002
 * Dave Ellis, SIXNET, [e-mail].
 *  Based on code by:
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 * and other contributors to U-Boot. See file CREDITS for list
 * of people who contributed to this  project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <config.h>
#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h>	/* for eth_init() */
#include <rtc.h>
#include "sixnet.h"
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
#endif

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

#define ORMASK(size) ((-size) & OR_AM_MSK)

static long ram_size(ulong *, long);

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress (int status)
{
#if defined(CONFIG_STATUS_LED)
# if defined(STATUS_LED_BOOT)
	if (status == 15) {
		/* ready to transfer to kernel, make sure LED is proper state */
		status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
	}
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}
#endif

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 * returns 0 if recognized, -1 if unknown
 */

int checkboard (void)
{
	puts ("Board: SIXNET SXNI855T\n");
	return 0;
}

/* ------------------------------------------------------------------------- */

#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
#endif	/* CFG_CMD_PCMCIA */

/* ------------------------------------------------------------------------- */

#define _not_used_ 0xffffffff

/* UPMB table for dual UART. */

/* this table is for 50MHz operation, it should work at all lower speeds */
const uint duart_table[] =
{
	/* single read. (offset 0 in upm RAM) */
	0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
	0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,

	/* burst read. (offset 8 in upm RAM) */
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
	0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,

	/* burst write. (offset 20 in upm RAM) */
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	_not_used_, _not_used_, _not_used_, _not_used_,
};

/* Load FPGA very early in boot sequence, since it must be
 * loaded before the 16C2550 serial channels can be used as
 * console channels.
 *
 * Note: Much of the configuration is not complete. The
 *       stack is in DPRAM since SDRAM has not been initialized,
 *       so the stack must be kept small. Global variables
 *       are still in FLASH, so they cannot be written.
 *	 Only the FLASH, DPRAM, immap and FPGA can be addressed,
 *       the other chip selects may not have been initialized.
 *       The clocks have been initialized, so udelay() can be
 *       used.
 */
#define FPGA_DONE	0x0080	/* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L	0x0040	/* PA9, output, low to reset, high to start */
#define FPGA_INIT_L	0x0020	/* PA10, input, low indicates not ready	*/
#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))	/* FPGA port */

int board_postclk_init (void)
{

	/* the data to load to the XCSxxXL FPGA */
	static const unsigned char fpgadata[] = {
# include "fpgadata.c"
	};

	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
	const unsigned char* pdata;

	/* /INITFPGA and DONEFPGA signals are inputs */
	immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);

	/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
	porta &= ~FPGA_PROGRAM_L;

	/* Set FPGA as an output */
	immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;

	/* delay a little to make sure FPGA sees it, really
	 * only need less than a microsecond.
	 */
	udelay(10);

	/* unassert /PROGRAM */
	porta |= FPGA_PROGRAM_L;

	/* delay while FPGA does last erase, indicated by
	 * /INITFPGA going high. This should happen within a
	 * few milliseconds.
	 */
	/* ### FIXME - a timeout check would be good, maybe flash
	 * the status LED to indicate the error?
	 */
	while ((porta & FPGA_INIT_L) == 0)
		; /* waiting */

	/* write program data to FPGA at the programming address
	 * so extra /CS1 strobes at end of configuration don't actually
	 * write to any registers.
	 */
	fpga = 0xff;		/* first write is ignored	*/
	fpga = 0xff;		/* fill byte			*/
	fpga = 0xff;		/* fill byte			*/
	fpga = 0x4f;		/* preamble code		*/
	fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
	fpga = 0x4b;		/* field check code */

	pdata = fpgadata;
	/* while no error write out each of the 28 byte frames */
	while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
	       && pdata < fpgadata + sizeof(fpgadata)) {

		fpga = 0x4f;	/* preamble code */

		/* 21 bytes of data in a frame */
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++); fpga = *(pdata++);
		fpga = *(pdata++);

		fpga = 0x4b;	/* field check code		*/
		fpga = 0xff;	/* extended write cycle		*/
		fpga = 0x4b;	/* extended write cycle
				 * (actually 0x4b from bitgen.exe)
				 */
		fpga = 0xff;	/* extended write cycle		*/
		fpga = 0xff;	/* extended write cycle		*/
		fpga = 0xff;	/* extended write cycle		*/
	}

	fpga = 0xff;		/* startup byte			*/
	fpga = 0xff;		/* startup byte			*/
	fpga = 0xff;		/* startup byte			*/
	fpga = 0xff;		/* startup byte			*/

#if 0 /* ### FIXME */
	/* If didn't load all the data or FPGA_DONE is low the load failed.
	 * Maybe someday stop here and flash the status LED? The console
	 * is not configured, so can't print an error message. Can't write
	 * global variables to set a flag (except gd?).
	 * For now it must work.
	 */
#endif

	/* Now that the FPGA is loaded, set up the Dual UART chip
	 * selects. Must be done here since it may be used as the console.
	 */
	upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));

	memctl->memc_mbmr = DUART_MBMR;
	memctl->memc_or5 = DUART_OR_VALUE;
	memctl->memc_br5 = DUART_BR5_VALUE;
	memctl->memc_or6 = DUART_OR_VALUE;
	memctl->memc_br6 = DUART_BR6_VALUE;

	return (0);
}

/* ------------------------------------------------------------------------- */

/* base address for SRAM, assume 32-bit port,  valid */
#define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)

/*  up to 64MB - will be adjusted for actual size */
#define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
	| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
 * Miscellaneous platform dependent initializations after running in RAM.
 */

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	char* s;
	char* e;
	int reg;
	bd_t *bd = gd->bd;

	memctl->memc_or2 = NVRAM_OR_PRELIM;
	memctl->memc_br2 = NVRAM_BR_VALUE;

	/* Is there any SRAM? Is it 16 or 32 bits wide? */

	/* First look for 32-bit SRAM */
	bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);

	if (bd->bi_sramsize == 0) {
	    /* no 32-bit SRAM, but there could be 16-bit SRAM since
	     * it would report size 0 when configured for 32-bit bus.
	     * Try again with a 16-bit bus.
	     */
	    memctl->memc_br2 |= BR_PS_16;
	    bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
	}

	if (bd->bi_sramsize == 0) {
	    memctl->memc_br2 = 0;	/* disable select since nothing there */
	}
	else {
	    /* adjust or2 for actual size of SRAM */
	    memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
	    bd->bi_sramstart = CFG_SRAM_BASE;
	    printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
	}


	/* set standard MPC8xx clock so kernel will see the time
	 * even if it doesn't have a DS1306 clock driver.
	 * This helps with experimenting with standard kernels.
	 */
	{
	    ulong tim;
	    struct rtc_time tmp;