fec.c

linux下的BOOT程序原码,有需要的可以来下,保证好用

	if (fec->xcv_type != SEVENWIRE)
		mpc8220_fec_phydump (dev->name);
#endif

	/*
	 * Enable SmartDMA receive task
	 */
	DMA_TASK_ENABLE (FEC_RECV_TASK_NO);

#ifdef DEBUG
	printf ("mpc8220_fec_init... Done \n");
#endif

	return 1;
}

/********************************************************************/
static void mpc8220_fec_halt (struct eth_device *dev)
{
	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
	int counter = 0xffff;

#ifdef DEBUG
	if (fec->xcv_type != SEVENWIRE)
		mpc8220_fec_phydump (dev->name);
#endif

	/*
	 * mask FEC chip interrupts
	 */
	fec->eth->imask = 0;

	/*
	 * issue graceful stop command to the FEC transmitter if necessary
	 */
	fec->eth->x_cntrl |= 0x00000001;

	/*
	 * wait for graceful stop to register
	 */
	while ((counter--) && (!(fec->eth->ievent & 0x10000000)));

	/*
	 * Disable SmartDMA tasks
	 */
	DMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
	DMA_TASK_DISABLE (FEC_RECV_TASK_NO);

	/*
	 * Disable the Ethernet Controller
	 */
	fec->eth->ecntrl &= 0xfffffffd;

	/*
	 * Clear FIFO status registers
	 */
	fec->eth->rfifo_status &= 0x00700000;
	fec->eth->tfifo_status &= 0x00700000;

	fec->eth->reset_cntrl = 0x01000000;

	/*
	 * Issue a reset command to the FEC chip
	 */
	fec->eth->ecntrl |= 0x1;

	/*
	 * wait at least 16 clock cycles
	 */
	udelay (10);

#ifdef DEBUG
	printf ("Ethernet task stopped\n");
#endif
}

#ifdef DEBUG
/********************************************************************/

static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
{
	u16 phyAddr = CONFIG_PHY_ADDR;
	u16 phyStatus;

	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
	    || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {

		miiphy_read (devname, phyAddr, 0x1, &phyStatus);
		printf ("\nphyStatus: 0x%04x\n", phyStatus);
		printf ("ecntrl:   0x%08x\n", fec->eth->ecntrl);
		printf ("ievent:   0x%08x\n", fec->eth->ievent);
		printf ("x_status: 0x%08x\n", fec->eth->x_status);
		printf ("tfifo: status	0x%08x\n", fec->eth->tfifo_status);

		printf ("	control 0x%08x\n", fec->eth->tfifo_cntrl);
		printf ("	lrfp	0x%08x\n", fec->eth->tfifo_lrf_ptr);
		printf ("	lwfp	0x%08x\n", fec->eth->tfifo_lwf_ptr);
		printf ("	alarm	0x%08x\n", fec->eth->tfifo_alarm);
		printf ("	readptr 0x%08x\n", fec->eth->tfifo_rdptr);
		printf ("	writptr 0x%08x\n", fec->eth->tfifo_wrptr);
	}
}

static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
{
	u16 phyAddr = CONFIG_PHY_ADDR;
	u16 phyStatus;

	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
	    || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {

		miiphy_read (devname, phyAddr, 0x1, &phyStatus);
		printf ("\nphyStatus: 0x%04x\n", phyStatus);
		printf ("ecntrl:   0x%08x\n", fec->eth->ecntrl);
		printf ("ievent:   0x%08x\n", fec->eth->ievent);
		printf ("x_status: 0x%08x\n", fec->eth->x_status);
		printf ("rfifo: status	0x%08x\n", fec->eth->rfifo_status);

		printf ("	control 0x%08x\n", fec->eth->rfifo_cntrl);
		printf ("	lrfp	0x%08x\n", fec->eth->rfifo_lrf_ptr);
		printf ("	lwfp	0x%08x\n", fec->eth->rfifo_lwf_ptr);
		printf ("	alarm	0x%08x\n", fec->eth->rfifo_alarm);
		printf ("	readptr 0x%08x\n", fec->eth->rfifo_rdptr);
		printf ("	writptr 0x%08x\n", fec->eth->rfifo_wrptr);
	}
}
#endif /* DEBUG */

/********************************************************************/

static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
			     int data_length)
{
	/*
	 * This routine transmits one frame.  This routine only accepts
	 * 6-byte Ethernet addresses.
	 */
	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
	FEC_TBD *pTbd;

#ifdef DEBUG
	printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
	tfifo_print (dev->name, fec);
#endif

	/*
	 * Clear Tx BD ring at first
	 */
	mpc8220_fec_tbd_scrub (fec);

	/*
	 * Check for valid length of data.
	 */
	if ((data_length > 1500) || (data_length <= 0)) {
		return -1;
	}

	/*
	 * Check the number of vacant TxBDs.
	 */
	if (fec->cleanTbdNum < 1) {
#ifdef DEBUG
		printf ("No available TxBDs ...\n");
#endif
		return -1;
	}

	/*
	 * Get the first TxBD to send the mac header
	 */
	pTbd = &fec->tbdBase[fec->tbdIndex];
	pTbd->dataLength = data_length;
	pTbd->dataPointer = (u32) eth_data;
	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;

#ifdef DEBUG
	printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
#endif

	/*
	 * Kick the MII i/f
	 */
	if (fec->xcv_type != SEVENWIRE) {
		u16 phyStatus;

		miiphy_read (dev->name, 0, 0x1, &phyStatus);
	}

	/*
	 * Enable SmartDMA transmit task
	 */

#ifdef DEBUG
	tfifo_print (dev->name, fec);
#endif

	DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);

#ifdef DEBUG
	tfifo_print (dev->name, fec);
#endif

#ifdef DEBUG
	printf ("+");
#endif

	fec->cleanTbdNum -= 1;

#ifdef DEBUG
	printf ("smartDMA ethernet Tx task enabled\n");
#endif
	/*
	 * wait until frame is sent .
	 */
	while (pTbd->status & FEC_TBD_READY) {
		udelay (10);
#ifdef DEBUG
		printf ("TDB status = %04x\n", pTbd->status);
#endif
	}

	return 0;
}


/********************************************************************/
static int mpc8220_fec_recv (struct eth_device *dev)
{
	/*
	 * This command pulls one frame from the card
	 */
	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
	FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
	unsigned long ievent;
	int frame_length, len = 0;
	NBUF *frame;

#ifdef DEBUG
	printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex);
	printf ("-");
#endif

	/*
	 * Check if any critical events have happened
	 */
	ievent = fec->eth->ievent;
	fec->eth->ievent = ievent;
	if (ievent & 0x20060000) {
		/* BABT, Rx/Tx FIFO errors */
		mpc8220_fec_halt (dev);
		mpc8220_fec_init (dev, NULL);
		return 0;
	}
	if (ievent & 0x80000000) {
		/* Heartbeat error */
		fec->eth->x_cntrl |= 0x00000001;
	}
	if (ievent & 0x10000000) {
		/* Graceful stop complete */
		if (fec->eth->x_cntrl & 0x00000001) {
			mpc8220_fec_halt (dev);
			fec->eth->x_cntrl &= ~0x00000001;
			mpc8220_fec_init (dev, NULL);
		}
	}

	if (!(pRbd->status & FEC_RBD_EMPTY)) {
		if ((pRbd->status & FEC_RBD_LAST)
		    && !(pRbd->status & FEC_RBD_ERR)
		    && ((pRbd->dataLength - 4) > 14)) {

			/*
			 * Get buffer address and size
			 */
			frame = (NBUF *) pRbd->dataPointer;
			frame_length = pRbd->dataLength - 4;

#if (0)
			{
				int i;

				printf ("recv data hdr:");
				for (i = 0; i < 14; i++)
					printf ("%x ", *(frame->head + i));
				printf ("\n");
			}
#endif
			/*
			 *  Fill the buffer and pass it to upper layers
			 */
/*			memcpy(buff, frame->head, 14);
			memcpy(buff + 14, frame->data, frame_length);*/
			NetReceive ((volatile uchar *) pRbd->dataPointer,
				    frame_length);
			len = frame_length;
		}
		/*
		 * Reset buffer descriptor as empty
		 */
		mpc8220_fec_rbd_clean (fec, pRbd);
	}
	DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
	return len;
}


/********************************************************************/
int mpc8220_fec_initialize (bd_t * bis)
{
	mpc8220_fec_priv *fec;

#ifdef CONFIG_HAS_ETH1
	mpc8220_fec_priv *fec2;
#endif
	struct eth_device *dev;
	char *tmp, *end;
	char env_enetaddr[6];

#ifdef CONFIG_HAS_ETH1
	char env_enet1addr[6];
#endif
	int i;

	fec = (mpc8220_fec_priv *) malloc (sizeof (*fec));
	dev = (struct eth_device *) malloc (sizeof (*dev));
	memset (dev, 0, sizeof *dev);

	fec->eth = (ethernet_regs *) MMAP_FEC1;
#ifdef CONFIG_HAS_ETH1
	fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec));
	fec2->eth = (ethernet_regs *) MMAP_FEC2;
#endif
	fec->tbdBase = (FEC_TBD *) FEC_BD_BASE;
	fec->rbdBase =
		(FEC_RBD *) (FEC_BD_BASE + FEC_TBD_NUM * sizeof (FEC_TBD));
	fec->xcv_type = MII100;

	dev->priv = (void *) fec;
	dev->iobase = MMAP_FEC1;
	dev->init = mpc8220_fec_init;
	dev->halt = mpc8220_fec_halt;
	dev->send = mpc8220_fec_send;
	dev->recv = mpc8220_fec_recv;

	sprintf (dev->name, "FEC ETHERNET");
	eth_register (dev);

#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
	miiphy_register (dev->name,
			fec8220_miiphy_read, fec8220_miiphy_write);
#endif

	/*
	 * Try to set the mac address now. The fec mac address is
	 * a garbage after reset. When not using fec for booting
	 * the Linux fec driver will try to work with this garbage.
	 */
	tmp = getenv ("ethaddr");
	if (tmp) {
		for (i = 0; i < 6; i++) {
			env_enetaddr[i] =
				tmp ? simple_strtoul (tmp, &end, 16) : 0;
			if (tmp)
				tmp = (*end) ? end + 1 : end;
		}
		mpc8220_fec_set_hwaddr (fec, env_enetaddr);
	}
#ifdef CONFIG_HAS_ETH1
	tmp = getenv ("eth1addr");
	if (tmp) {
		for (i = 0; i < 6; i++) {
			env_enet1addr[i] =
				tmp ? simple_strtoul (tmp, &end, 16) : 0;
			if (tmp)
				tmp = (*end) ? end + 1 : end;
		}
		mpc8220_fec_set_hwaddr (fec2, env_enet1addr);
	}
#endif

	return 1;
}

/* MII-interface related functions */
/********************************************************************/
int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
	ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
	u32 reg;		/* convenient holder for the PHY register */
	u32 phy;		/* convenient holder for the PHY */
	int timeout = 0xffff;

	/*
	 * reading from any PHY's register is done by properly
	 * programming the FEC's MII data register.
	 */
	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;

	eth->mii_data =
		(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy
		 | reg);

	/*
	 * wait for the related interrupt
	 */
	while ((timeout--) && (!(eth->ievent & 0x00800000)));

	if (timeout == 0) {
#ifdef DEBUG
		printf ("Read MDIO failed...\n");
#endif
		return -1;
	}

	/*
	 * clear mii interrupt bit
	 */
	eth->ievent = 0x00800000;

	/*
	 * it's now safe to read the PHY's register
	 */
	*retVal = (u16) eth->mii_data;

	return 0;
}

/********************************************************************/
int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
	ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
	u32 reg;		/* convenient holder for the PHY register */
	u32 phy;		/* convenient holder for the PHY */
	int timeout = 0xffff;

	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;

	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
			 FEC_MII_DATA_TA | phy | reg | data);

	/*
	 * wait for the MII interrupt
	 */
	while ((timeout--) && (!(eth->ievent & 0x00800000)));

	if (timeout == 0) {
#ifdef DEBUG
		printf ("Write MDIO failed...\n");
#endif
		return -1;
	}

	/*
	 * clear MII interrupt bit
	 */
	eth->ievent = 0x00800000;

	return 0;
}

#ifdef DEBUG
static u32 local_crc32 (char *string, unsigned int crc_value, int len)
{
	int i;
	char c;
	unsigned int crc, count;

	/*
	 * crc32 algorithm
	 */
	/*
	 * crc = 0xffffffff; * The initialized value should be 0xffffffff
	 */
	crc = crc_value;

	for (i = len; --i >= 0;) {
		c = *string++;
		for (count = 0; count < 8; count++) {
			if ((c & 0x01) ^ (crc & 0x01)) {
				crc >>= 1;
				crc = crc ^ 0xedb88320;
			} else {
				crc >>= 1;
			}
			c >>= 1;
		}
	}

	/*
	 * In big endian system, do byte swaping for crc value
	 */
	return crc;
}
#endif /* DEBUG */

#endif /* CONFIG_MPC8220_FEC */