immap_83xx.h

linux下的BOOT程序原码,有需要的可以来下,保证好用

/*
 * I2C1 Controller
 */


/*
 * DUART
 */
typedef struct duart8349{
	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
	u8 uier_udmb;      /**< combined register for UIER and UDMB */
	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
	u8 ulcr;        /**< line control register */
	u8 umcr;        /**< MODEM control register */
	u8 ulsr;        /**< line status register */
	u8 umsr;        /**< MODEM status register */
	u8 uscr;        /**< scratch register */
	u8 res0[8];
	u8 udsr;        /**< DMA status register */
	u8 res1[3];
	u8 res2[0xEC];
} duart8349_t;

/*
 * Local Bus Controller Registers
 */
typedef struct lbus_bank{
	u32 br;             /**< Base Register  */
	u32 or;             /**< Base Register  */
} lbus_bank_t;

typedef struct lbus8349 {
	lbus_bank_t bank[8];
	u8 res0[0x28];
	u32 mar;                /**< UPM Address Register */
	u8 res1[0x4];
	u32 mamr;               /**< UPMA Mode Register */
	u32 mbmr;               /**< UPMB Mode Register */
	u32 mcmr;               /**< UPMC Mode Register */
	u8 res2[0x8];
	u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
	u32 mdr;                /**< UPM Data Register */
	u8 res3[0x8];
	u32 lsdmr;              /**< SDRAM Mode Register */
	u8 res4[0x8];
	u32 lurt;               /**< UPM Refresh Timer */
	u32 lsrt;               /**< SDRAM Refresh Timer */
	u8 res5[0x8];
	u32 ltesr;              /**< Transfer Error Status Register */
	u32 ltedr;              /**< Transfer Error Disable Register */
	u32 lteir;              /**< Transfer Error Interrupt Register */
	u32 lteatr;             /**< Transfer Error Attributes Register */
	u32 ltear;              /**< Transfer Error Address Register */
	u8 res6[0xC];
	u32 lbcr;               /**< Configuration Register */
#define LBCR_LDIS  0x80000000
#define LBCR_LDIS_SHIFT    31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT   22
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT   17
#define LBCR_EPAR  0x00010000
#define LBCR_EPAR_SHIFT    16
#define LBCR_BMT   0x0000FF00
#define LBCR_BMT_SHIFT      8
	u32 lcrr;               /**< Clock Ratio Register */
#define LCRR_DBYP    0x80000000
#define LCRR_DBYP_SHIFT      31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT   28
#define LCRR_ECL     0x03000000
#define LCRR_ECL_SHIFT       24
#define LCRR_EADC    0x00030000
#define LCRR_EADC_SHIFT      16
#define LCRR_CLKDIV  0x0000000F
#define LCRR_CLKDIV_SHIFT     0


	u8 res7[0x28];
	u8 res8[0xF00];
} lbus8349_t;

/*
 * Serial Peripheral Interface
 */
typedef struct spi8349
{
	u32 mode;     /**< mode register  */
	u32 event;    /**< event register */
	u32 mask;     /**< mask register  */
	u32 com;      /**< command register */
	u8 res0[0x10];
	u32 tx;       /**< transmit register */
	u32 rx;       /**< receive register */
	u8 res1[0xD8];
} spi8349_t;

typedef struct dma8349 {
	u8 fixme[0x300];
} dma8349_t;

/*
 * PCI Software Configuration Registers
 */
typedef struct pciconf8349 {
	u32	config_address;
#define PCI_CONFIG_ADDRESS_EN	0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
	u32 config_data;
	u32 int_ack;
	u8	res[116];
} pciconf8349_t;

/*
 * PCI Outbound Translation Register
 */
typedef struct pci_outbound_window {
	u32	potar;
	u8	res0[4];
	u32	pobar;
	u8	res1[4];
	u32	pocmr;
	u8	res2[4];
} pot8349_t;
/*
 * Sequencer
 */
typedef struct ios8349 {
	pot8349_t	pot[6];
#define POTAR_TA_MASK	0x000fffff
#define	POBAR_BA_MASK	0x000fffff
#define	POCMR_EN	0x80000000
#define	POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
#define	POCMR_SE	0x20000000	/* streaming enable */
#define	POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2*/
#define	POCMR_CM_MASK	0x000fffff
#define	POCMR_CM_4G	0x00000000
#define	POCMR_CM_2G	0x00080000
#define	POCMR_CM_1G	0x000C0000
#define	POCMR_CM_512M	0x000E0000
#define	POCMR_CM_256M	0x000F0000
#define	POCMR_CM_128M	0x000F8000
#define	POCMR_CM_64M	0x000FC000
#define	POCMR_CM_32M	0x000FE000
#define	POCMR_CM_16M	0x000FF000
#define	POCMR_CM_8M	0x000FF800
#define	POCMR_CM_4M	0x000FFC00
#define	POCMR_CM_2M	0x000FFE00
#define	POCMR_CM_1M	0x000FFF00
#define	POCMR_CM_512K	0x000FFF80
#define	POCMR_CM_256K	0x000FFFC0
#define	POCMR_CM_128K	0x000FFFE0
#define	POCMR_CM_64K	0x000FFFF0
#define	POCMR_CM_32K	0x000FFFF8
#define	POCMR_CM_16K	0x000FFFFC
#define	POCMR_CM_8K	0x000FFFFE
#define	POCMR_CM_4K	0x000FFFFF
	u8	res0[0x60];
	u32	pmcr;
	u8	res1[4];
	u32	dtcr;
	u8	res2[4];
} ios8349_t;

/*
 * PCI Controller Control and Status Registers
 */
typedef struct pcictrl8349 {
	u32	esr;
#define ESR_MERR	0x80000000
#define ESR_APAR	0x00000400
#define	ESR_PCISERR	0x00000200
#define	ESR_MPERR	0x00000100
#define	ESR_TPERR	0x00000080
#define	ESR_NORSP	0x00000040
#define	ESR_TABT	0x00000020
	u32	ecdr;
#define ECDR_APAR	0x00000400
#define	ECDR_PCISERR	0x00000200
#define	ECDR_MPERR	0x00000100
#define	ECDR_TPERR	0x00000080
#define	ECDR_NORSP	0x00000040
#define	ECDR_TABT	0x00000020
	u32 eer;
#define EER_APAR	0x00000400
#define	EER_PCISERR	0x00000200
#define	EER_MPERR	0x00000100
#define	EER_TPERR	0x00000080
#define	EER_NORSP	0x00000040
#define	EER_TABT	0x00000020
	u32	eatcr;
#define	EATCR_ERRTYPR_MASK	0x70000000
#define	EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
#define	EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
#define	EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
#define	EATCR_ERRTYPR_MA	0x30000000	/* master abort */
#define	EATCR_ERRTYPR_TA	0x40000000	/* target abort */
#define	EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
#define	EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
#define	EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
#define EATCR_BN_MASK		0x0f000000	/* beat number */
#define	EATCR_BN_1st		0x00000000
#define	EATCR_BN_2ed		0x01000000
#define	EATCR_BN_3rd		0x02000000
#define	EATCR_BN_4th		0x03000000
#define	EATCR_BN_5th		0x0400000
#define	EATCR_BN_6th		0x05000000
#define	EATCR_BN_7th		0x06000000
#define	EATCR_BN_8th		0x07000000
#define	EATCR_BN_9th		0x08000000
#define EATCR_TS_MASK		0x00300000	/* transaction size */
#define	EATCR_TS_4		0x00000000
#define	EATCR_TS_1		0x00100000
#define	EATCR_TS_2		0x00200000
#define	EATCR_TS_3		0x00300000
#define	EATCR_ES_MASK		0x000f0000	/* error source */
#define	EATCR_ES_EM		0x00000000	/* external master */
#define	EATCR_ES_DMA		0x00050000
#define	EATCR_CMD_MASK		0x0000f000
#define	EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable*/
#define	EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
#define	EATCR_HPB		0x00000004	/* high parity bit */
#define	EATCR_PB		0x00000002	/* parity bit*/
#define	EATCR_VI		0x00000001	/* error information valid */
	u32	eacr;
	u32	eeacr;
	u32	edlcr;
	u32	edhcr;
	u32	gcr;
	u32	ecr;
	u32	gsr;
	u8	res0[12];
	u32	pitar2;
	u8	res1[4];
	u32	pibar2;
	u32	piebar2;
	u32	piwar2;
	u8	res2[4];
	u32	pitar1;
	u8	res3[4];
	u32	pibar1;
	u32	piebar1;
	u32	piwar1;
	u8	res4[4];
	u32	pitar0;
	u8	res5[4];
	u32	pibar0;
	u8	res6[4];
	u32	piwar0;
	u8	res7[132];
#define PITAR_TA_MASK		0x000fffff
#define PIBAR_MASK		0xffffffff
#define PIEBAR_EBA_MASK		0x000fffff
#define PIWAR_EN		0x80000000
#define PIWAR_PF		0x20000000
#define	PIWAR_RTT_MASK		0x000f0000
#define	PIWAR_RTT_NO_SNOOP	0x00040000
#define PIWAR_RTT_SNOOP		0x00050000
#define	PIWAR_WTT_MASK		0x0000f000
#define	PIWAR_WTT_NO_SNOOP	0x00004000
#define PIWAR_WTT_SNOOP		0x00005000
#define	PIWAR_IWS_MASK	0x0000003F
#define	PIWAR_IWS_4K	0x0000000B
#define	PIWAR_IWS_8K	0x0000000C
#define	PIWAR_IWS_16K	0x0000000D
#define	PIWAR_IWS_32K	0x0000000E
#define	PIWAR_IWS_64K	0x0000000F
#define	PIWAR_IWS_128K	0x00000010
#define	PIWAR_IWS_256K	0x00000011
#define	PIWAR_IWS_512K	0x00000012
#define	PIWAR_IWS_1M	0x00000013
#define	PIWAR_IWS_2M	0x00000014
#define	PIWAR_IWS_4M	0x00000015
#define	PIWAR_IWS_8M	0x00000016
#define	PIWAR_IWS_16M	0x00000017
#define	PIWAR_IWS_32M	0x00000018
#define	PIWAR_IWS_64M	0x00000019
#define	PIWAR_IWS_128M	0x0000001A
#define	PIWAR_IWS_256M	0x0000001B
#define	PIWAR_IWS_512M	0x0000001C
#define	PIWAR_IWS_1G	0x0000001D
#define	PIWAR_IWS_2G	0x0000001E
} pcictrl8349_t;

/*
 * USB
 */
typedef struct usb8349 {
	u8 fixme[0x2000];
} usb8349_t;

/*
 * TSEC
 */
typedef struct tsec8349 {
	u8 fixme[0x1000];
} tsec8349_t;

/*
 * Security
 */
typedef struct security8349 {
	u8 fixme[0x10000];
} security8349_t;

typedef struct immap {
	sysconf8349_t sysconf; /* System configuration */
	wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
	rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
	rtclk8349_t   pit;     /* Periodic Interval Timer */
	gtm8349_t     gtm[2];  /* Global Timers Module */
	ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
	arbiter8349_t arbiter; /* System Arbiter Registers */
	reset8349_t   reset;   /* Reset Module */
	clk8349_t     clk;     /* System Clock Module */
	pmc8349_t     pmc;     /* Power Management Control Module */
	gpio8349_t    pgio[2]; /* general purpose I/O module */
	u8 res0[0x200];
	u8 DDL_DDR[0x100];
	u8 DDL_LBIU[0x100];
	u8 res1[0xE00];
	ddr8349_t     ddr;     /* DDR Memory Controller Memory */
	i2c_t     i2c[2];      /* I2C1 Controller */
	u8 res2[0x1300];
	duart8349_t   duart[2];/* DUART */
	u8 res3[0x900];
	lbus8349_t    lbus;    /* Local Bus Controller Registers */
	u8 res4[0x1000];
	spi8349_t     spi;     /* Serial Peripheral Interface */
	u8 res5[0xF00];
	dma8349_t     dma;     /* DMA */
	pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
	ios8349_t     ios;     /* Sequencer */
	pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
	u8 res6[0x19900];
	usb8349_t     usb;
	tsec8349_t    tsec[2];
	u8 res7[0xA000];
	security8349_t security;
} immap_t;

#endif /* __IMMAP_8349__ */