immap_83xx.h

linux下的BOOT程序原码,有需要的可以来下,保证好用

#define SERR_MU   0x01000000 /*  MU MCP request  */
#define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
			|SERR_RNC )
	u32    sercr; /*  System Error Control Register  (SERCR)  */
#define SERCR_MCPR 0x00000001 /*  MCP Route  */
#define SERCR_RES ~(SERCR_MCPR)
	u8    res2[4];
	u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
	u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
	u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
	u32   serfr;   /*  System Error Force Register (SERR)  */
	u8    res3[0xA0];
} ipic8349_t;

/*
 * System Arbiter Registers
 */
typedef struct arbiter8349 {
	u32 acr; /* Arbiter Configuration Register */
#define ACR_COREDIS    0x10000000 /* Core disable. */
#define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
#define ACR_RPTCNT     0x00000700 /* Repeat count. */
#define ACR_APARK      0x00000030 /* Address parking. */
#define ACR_PARKM	   0x0000000F /* Parking master. */
#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
	u32 atr; /* Arbiter Timers Register */
#define ATR_DTO 0x00FF0000 /* Data time out. */
#define ATR_ATO	0x000000FF /* Address time out. */
#define ATR_RES ~(ATR_DTO|ATR_ATO)
	u8 res[4];
	u32 aer; /* Arbiter Event Register (AE)*/
	u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
	u32 amr; /* Arbiter Mask Register (AE) */
	u32 aeatr; /* Arbiter Event Attributes Register */
#define AEATR_EVENT   0x07000000 /* Event type. */
#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
#define AEATR_TBST    0x00000800 /* Transfer burst. */
#define AEATR_TSIZE   0x00000700 /* Transfer Size. */
#define AEATR_TTYPE	  0x0000001F /* Transfer Type. */
#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
	u32 aeadr; /* Arbiter Event Address Register */
	u32 aerr; /* Arbiter Event Response Register (AE)*/
#define AE_ETEA 0x00000020 /* Transfer error. */
#define AE_RES_ 0x00000010 /* Reserved transfer type. */
#define AE_ECW  0x00000008 /* External control word transfer type. */
#define AE_AO   0x00000004 /* Address Only transfer type. */
#define AE_DTO  0x00000002 /* Data time out. */
#define AE_ATO	0x00000001 /* Address time out. */
#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
	u8 res1[0xDC];
} arbiter8349_t;

/*
 * Reset Module
 */
typedef struct reset8349 {
	u32    rcwl; /* RCWL Register  */
#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
#define RCWL_LBIUCM_SHIFT    31
#define RCWL_DDRCM   0x40000000 /* DDRCM  */
#define RCWL_DDRCM_SHIFT     30
#define RCWL_SVCOD   0x30000000 /* SVCOD  */
#define RCWL_SPMF    0x0f000000 /* SPMF  */
#define RCWL_SPMF_SHIFT      24
#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
#define RCWL_COREPLL_SHIFT   16
#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
#define RCWL_CEPDF   0x00000020 /* CEPDF  */
#define RCWL_CEPMF   0x0000001F /* CEPMF  */
#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
	u32    rcwh; /* RCHL Register  */
#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
#define RCWH_PCIHOST_SHIFT   31
#define RCWH_PCI64   0x40000000 /* PCI64  */
#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
#define RCWH_COREDIS 0x08000000 /* COREDIS  */
#define RCWH_BMS     0x04000000 /* BMS  */
#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
#define RCWH_SWEN    0x00800000 /* SWEN  */
#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
#define RCWH_TPR     0x00000100 /* TPR  */
#define RCWH_TLE     0x00000008 /* TLE  */
#define RCWH_LALE    0x00000004 /* LALE  */
#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
			| RCWH_TLE | RCWH_LALE)
	u8     res0[8];
	u32    rsr; /* Reset status Register  */
#define RSR_RSTSRC 0xE0000000 /* Reset source  */
#define RSR_RSTSRC_SHIFT   29
#define RSR_BSF    0x00010000 /* Boot seq. fail  */
#define RSR_BSF_SHIFT      16
#define RSR_SWSR   0x00002000 /* software soft reset  */
#define RSR_SWSR_SHIFT     13
#define RSR_SWHR   0x00001000 /* software hard reset  */
#define RSR_SWHR_SHIFT     12
#define RSR_JHRS   0x00000200 /* jtag hreset  */
#define RSR_JHRS_SHIFT      9
#define RSR_JSRS   0x00000100 /* jtag sreset status  */
#define RSR_JSRS_SHIFT      8
#define RSR_CSHR   0x00000010 /* checkstop reset status  */
#define RSR_CSHR_SHIFT      4
#define RSR_SWRS   0x00000008 /* software watchdog reset status  */
#define RSR_SWRS_SHIFT      3
#define RSR_BMRS   0x00000004 /* bus monitop reset status  */
#define RSR_BMRS_SHIFT      2
#define RSR_SRS    0x00000002 /* soft reset status  */
#define RSR_SRS_SHIFT       1
#define RSR_HRS    0x00000001 /* hard reset status  */
#define RSR_HRS_SHIFT       0
#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
	u32    rmr; /* Reset mode Register  */
#define RMR_CSRE   0x00000001 /* checkstop reset enable  */
#define RMR_CSRE_SHIFT      0
#define RMR_RES ~(RMR_CSRE)
	u32    rpr; /* Reset protection Register  */
	u32    rcr; /* Reset Control Register  */
#define RCR_SWHR 0x00000002 /* software hard reset  */
#define RCR_SWSR 0x00000001 /* software soft reset  */
#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
	u32    rcer; /* Reset Control Enable Register  */
#define RCER_CRE 0x00000001 /* software hard reset  */
#define RCER_RES ~(RCER_CRE)
	u8     res1[0xDC];
} reset8349_t;

typedef struct clk8349 {
	u32    spmr; /* system PLL mode Register  */
#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
#define SPMR_DDRCM   0x40000000 /* DDRCM  */
#define SPMR_SVCOD   0x30000000 /* SVCOD  */
#define SPMR_SPMF    0x0F000000 /* SPMF  */
#define SPMR_CKID    0x00800000 /* CKID  */
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
#define SPMR_CEPDF   0x00000020 /* CEPDF  */
#define SPMR_CEPMF   0x0000001F /* CEPMF  */
#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
	u32    occr; /* output clock control Register  */
#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
#define OCCR_PCICD0  0x00800000 /* PCICD0  */
#define OCCR_PCICD1  0x00400000 /* PCICD1  */
#define OCCR_PCICD2  0x00200000 /* PCICD2  */
#define OCCR_PCICD3  0x00100000 /* PCICD3  */
#define OCCR_PCICD4  0x00080000 /* PCICD4  */
#define OCCR_PCICD5  0x00040000 /* PCICD5  */
#define OCCR_PCICD6  0x00020000 /* PCICD6  */
#define OCCR_PCICD7  0x00010000 /* PCICD7  */
#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
	u32    sccr; /* system clock control Register  */
#define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_ENCCM    0x03000000 /* ENCCM  */
#define SCCR_ENCCM_SHIFT 24
#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_PCICM    0x00010000 /* PCICM  */
#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
	u8     res0[0xF4];
} clk8349_t;

/*
 * Power Management Control Module
 */
typedef struct pmc8349 {
	u32    pmccr; /* PMC Configuration Register  */
#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
	u32    pmcer; /* PMC Event Register  */
#define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
#define PMCER_RES ~(PMCER_PMCI)
	u32    pmcmr; /* PMC Mask Register  */
#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
#define PMCMR_RES ~(PMCMR_PMCIE)
	u8 res0[0xF4];
} pmc8349_t;


/*
 * general purpose I/O module
 */
typedef struct gpio8349 {
	u32 dir; /* direction register */
	u32 odr; /* open drain register */
	u32 dat; /* data register */
	u32 ier; /* interrupt event register */
	u32 imr; /* interrupt mask register */
	u32 icr; /* external interrupt control register */
	u8 res0[0xE8];
} gpio8349_t;

/*
 * DDR Memory Controller Memory Map
 */
typedef struct ddr_cs_bnds{
	u32 csbnds;
#define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT    8
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT   24
	u8  res0[4];
} ddr_cs_bnds_t;

typedef struct ddr8349{
	ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */
	u8 res0[0x60];
	u32 cs_config[4];       /**< Chip Select x Configuration */
#define CSCONFIG_EN         0x80000000
#define CSCONFIG_AP         0x00800000
#define CSCONFIG_ROW_BIT    0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
#define CSCONFIG_ROW_BIT_14 0x00000200
#define CSCONFIG_COL_BIT    0x00000007
#define CSCONFIG_COL_BIT_8  0x00000000
#define CSCONFIG_COL_BIT_9  0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
	u8 res1[0x78];
	u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT   28
#define TIMING_CFG1_ACTTOPRE 0x0F000000
#define TIMING_CFG1_ACTTOPRE_SHIFT   24
#define TIMING_CFG1_ACTTORW  0x00700000
#define TIMING_CFG1_ACTTORW_SHIFT    20
#define TIMING_CFG1_CASLAT   0x00070000
#define TIMING_CFG1_CASLAT_SHIFT     16
#define TIMING_CFG1_REFREC   0x0000F000
#define TIMING_CFG1_REFREC_SHIFT     12
#define TIMING_CFG1_WRREC    0x00000700
#define TIMING_CFG1_WRREC_SHIFT       8
#define TIMING_CFG1_ACTTOACT 0x00000070
#define TIMING_CFG1_ACTTOACT_SHIFT    4
#define TIMING_CFG1_WRTORD   0x00000007
#define TIMING_CFG1_WRTORD_SHIFT      0
#define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */

	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO           0x0F000000
#define TIMING_CFG2_CPO_SHIFT             24
#define TIMING_CFG2_ACSM          0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
#define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */

	u32 sdram_cfg;          /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN     0x80000000
#define SDRAM_CFG_SREN       0x40000000
#define SDRAM_CFG_ECC_EN     0x20000000
#define SDRAM_CFG_RD_EN      0x10000000
#define SDRAM_CFG_SDRAM_TYPE 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
#define SDRAM_CFG_DYN_PWR    0x00200000
#define SDRAM_CFG_32_BE      0x00080000
#define SDRAM_CFG_8_BE       0x00040000
#define SDRAM_CFG_NCAP       0x00020000
#define SDRAM_CFG_2T_EN      0x00008000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000

	u8 res2[4];
	u32 sdram_mode;         /**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT   16
#define SDRAM_MODE_SD  0x0000FFFF
#define SDRAM_MODE_SD_SHIFT     0
#define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
#define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
#define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
#define DDR_MODE_WEAK           0x0002  /* weak drivers */
#define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
#define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
#define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
#define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
#define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
#define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
#define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
#define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
#define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG        0x0000  /* select mode register */

	u8 res3[8];
	u32 sdram_interval;     /**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_REFINT  0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT    16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
	u8   res9[8];
	u32  sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000

	u8 res4[0xCCC];
	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
	u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
	u8 res5[0x14];
	u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
	u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
	u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
	u8 res6[0x14];
	u32 err_detect;         /**< Memory Error Detect */
	u32 err_disable;        /**< Memory Error Disable */
	u32 err_int_en;         /**< Memory Error Interrupt Enable */
	u32 capture_attributes; /**< Memory Error Attributes Capture */
	u32 capture_address;    /**< Memory Error Address Capture */
	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
	u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
	u8 res7[0xA4];
	u32 debug_reg;
	u8 res8[0xFC];
} ddr8349_t;