immap_83xx.h

linux下的BOOT程序原码,有需要的可以来下,保证好用

/*
 * MPC8349 Internal Memory Map
 * Copyright (c) 2004 Freescale Semiconductor.
 * Eran Liberty ([e-mail])
 *
 * based on:
 * - MPC8260 Internal Memory Map
 *   Copyright (c) 1999 Dan Malek ([e-mail])
 * - MPC85xx Internal Memory Map
 *   Copyright(c) 2002,2003 Motorola Inc.
 *   Xianghua Xiao ([e-mail])
 */
#ifndef __IMMAP_8349__
#define __IMMAP_8349__

#include <asm/types.h>
#include <asm/i2c.h>

/*
 * Local Access Window.
 */
typedef struct law8349 {
	u32 bar; /* LBIU local access window base address register */
/* Identifies the 20 most-significant address bits of the base of local
 * access window n. The specified base address should be aligned to the
 * window size, as defined by LBLAWARn[SIZE].
 */
#define LAWBAR_BAR         0xFFFFF000
#define LAWBAR_RES	     ~(LAWBAR_BAR)
	u32 ar; /* LBIU local access window attribute register */
} law8349_t;

/*
 * System configuration registers.
 */
typedef struct sysconf8349 {
	u32 immrbar; /* Internal memory map base address register */
	u8 res0[0x04];
	u32 altcbar; /* Alternate configuration base address register */
/* Identifies the12 most significant address bits of an alternate base
 * address used for boot sequencer configuration accesses.
 */
#define ALTCBAR_BASE_ADDR     0xFFF00000
#define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
	u8 res1[0x14];
	law8349_t lblaw[4]; /* LBIU local access window */
	u8 res2[0x20];
	law8349_t pcilaw[2]; /* PCI local access window */
	u8 res3[0x30];
	law8349_t ddrlaw[2]; /* DDR local access window */
	u8 res4[0x50];
	u32 sgprl; /* System General Purpose Register Low */
	u32 sgprh; /* System General Purpose Register High */
	u32 spridr; /* System Part and Revision ID Register */
#define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
#define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
	u8 res5[0x04];
	u32 spcr; /* System Priority Configuration Register */
#define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
#define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
#define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
#define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
#define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
#define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
#define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
#define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
	u32 sicrl; /* System General Purpose Register Low */
#define SICRL_LDP_A   0x80000000
#define SICRL_USB0    0x40000000
#define SICRL_USB1    0x20000000
#define SICRL_UART    0x0C000000
#define SICRL_GPIO1_A 0x02000000
#define SICRL_GPIO1_B 0x01000000
#define SICRL_GPIO1_C 0x00800000
#define SICRL_GPIO1_D 0x00400000
#define SICRL_GPIO1_E 0x00200000
#define SICRL_GPIO1_F 0x00180000
#define SICRL_GPIO1_G 0x00040000
#define SICRL_GPIO1_H 0x00020000
#define SICRL_GPIO1_I 0x00010000
#define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000
#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
	u32 sicrh; /* System General Purpose Register High */
#define SICRH_DDR     0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC1_C 0x04000000
#define SICRH_TSEC1_D 0x02000000
#define SICRH_TSEC1_E 0x01000000
#define SICRH_TSEC1_F 0x00800000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TSEC2_F 0x00020000
#define SICRH_TSEC2_G 0x00010000
#define SICRH_TSEC2_H 0x00008000
#define SICRH_GPIO2_A 0x00004000
#define SICRH_GPIO2_B 0x00002000
#define SICRH_GPIO2_C 0x00001000
#define SICRH_GPIO2_D 0x00000800
#define SICRH_GPIO2_E 0x00000400
#define SICRH_GPIO2_F 0x00000200
#define SICRH_GPIO2_G 0x00000180
#define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1  0x00000002
#define SICRH_TSOBI2  0x00000001
#define SICRh_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
			| SICRH_TSOBI2)
	u8 res6[0xE4];
} sysconf8349_t;

/*
 * Watch Dog Timer (WDT) Registers
 */
typedef struct wdt8349 {
	u8 res0[4];
	u32 swcrr; /* System watchdog control register */
	u32 swcnr; /* System watchdog count register */
#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
#define SWCNR_RES  ~(SWCNR_SWCN)
	u8 res1[2];
	u16 swsrr; /* System watchdog service register */
	u8 res2[0xF0];
} wdt8349_t;

/*
 * RTC/PIT Module Registers
 */
typedef struct rtclk8349 {
	u32 cnr; /* control register */
#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
#define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
#define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
#define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
#define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
	u32 ldr; /* load register */
	u32 psr; /* prescale register */
	u32 ctr; /* register */
	u32 evr; /* event register */
#define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
#define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
#define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
	u32 alr; /* alarm register */
	u8 res0[0xE8];
} rtclk8349_t;

/*
 * Global timper module
 */

typedef struct gtm8349 {
	u8    cfr1; /* Timer1/2 Configuration  */
#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
#define CFR1_BCM  0x40  /* Backward compatible mode  */
#define CFR1_STP2 0x20 /* Stop timer  */
#define CFR1_RST2 0x10 /* Reset timer  */
#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
#define CFR1_STP1 0x02 /* Stop timer  */
#define CFR1_RST1 0x01 /* Reset timer  */
	u8    res0[3];
	u8    cfr2; /* Timer3/4 Configuration  */
#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
#define CFR2_SCAS 0x40 /* Super Cascade mode  */
#define CFR2_STP4 0x20 /* Stop timer  */
#define CFR2_RST4 0x10 /* Reset timer  */
#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
#define CFR2_STP3 0x02 /* Stop timer  */
#define CFR2_RST3 0x01 /* Reset timer  */
	u8    res1[10];
	u16   mdr1; /* Timer1 Mode Register  */
#define MDR_SPS  0xff00 /* Secondary Prescaler value  */
#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
#define MDR_OM   0x0020 /* Output mode  */
#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
#define MDR_FRR  0x0008 /* Free run/restart  */
#define MDR_ICLK 0x0006 /* Input clock source for the timer  */
#define MDR_GE   0x0001 /* Gate enable  */
	u16   mdr2; /* Timer2 Mode Register  */
	u16   rfr1; /* Timer1 Reference Register  */
	u16   rfr2; /* Timer2 Reference Register  */
	u16   cpr1; /* Timer1 Capture Register  */
	u16   cpr2; /* Timer2 Capture Register  */
	u16   cnr1; /* Timer1 Counter Register  */
	u16   cnr2; /* Timer2 Counter Register  */
	u16   mdr3; /* Timer3 Mode Register  */
	u16   mdr4; /* Timer4 Mode Register  */
	u16   rfr3; /* Timer3 Reference Register  */
	u16   rfr4; /* Timer4 Reference Register  */
	u16   cpr3; /* Timer3 Capture Register  */
	u16   cpr4; /* Timer4 Capture Register  */
	u16   cnr3; /* Timer3 Counter Register  */
	u16   cnr4; /* Timer4 Counter Register  */
	u16   evr1; /* Timer1 Event Register  */
	u16   evr2; /* Timer2 Event Register  */
	u16   evr3; /* Timer3 Event Register  */
	u16   evr4; /* Timer4 Event Register  */
#define GTEVR_REF 0x0002 /* Output reference event  */
#define GTEVR_CAP 0x0001 /* Counter Capture event   */
#define GTEVR_RES ~(EVR_CAP|EVR_REF)
	u16   psr1; /* Timer1 Prescaler Register  */
	u16   psr2; /* Timer2 Prescaler Register  */
	u16   psr3; /* Timer3 Prescaler Register  */
	u16   psr4; /* Timer4 Prescaler Register  */
	u8    res[0xC0];
} gtm8349_t;

/*
 * Integrated Programmable Interrupt Controller
 */
typedef struct ipic8349 {
	u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
#define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
#define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
#define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
#define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
#define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
#define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
	u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
#define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
#define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
	u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
#define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
			| SIIH_I2C2 | SIIH_SPI)
	u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
#define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
#define SIIL_PIT   0x40000000 /*  PIT interrupt  */
#define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
#define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
#define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
#define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
#define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
#define SIIL_DMA   0x01000000 /*  DMA interrupt  */
#define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
#define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
#define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
#define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
#define SIIL_DDR   0x00080000 /*  DDR interrupt  */
#define SIIL_LBC   0x00040000 /*  LBC interrupt  */
#define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
#define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
#define SIIL_PMC   0x00008000 /*  PMC interrupt  */
#define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
#define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
#define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
#define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
#define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
			| SIIL_GTM5 |SIIL_DPTC )
	u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
	u8     res0[8];
	u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
	u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
	u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
	u8     res1[4];
	u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
	u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
	u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
	u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
#define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
#define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
#define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
#define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
#define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
#define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
#define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
#define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
#define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
			| SEI_SIRQ0)
	u32    secnr; /*  System External Interrupt Control Register (SECNR) */
#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
	u32   sersr; /*  System Error Status Register (SERR)  */
	u32   sermr; /*  System Error Mask Register (SERR)  */
#define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
#define SERR_WDT  0x40000000 /*  WDT MCP request  */
#define SERR_SBA  0x20000000 /*  SBA MCP request  */
#define SERR_DDR  0x10000000 /*  DDR MCP request  */
#define SERR_LBC  0x08000000 /*  LBC MCP request  */
#define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
#define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */