immap_85xx.h

linux下的BOOT程序原码,有需要的可以来下,保证好用

/*
 * L2 Cache Registers(0x2_0000-0x2_1000)
 */
typedef struct ccsr_l2cache {
	uint	l2ctl;		/* 0x20000 - L2 configuration register 0 */
	char	res1[12];
	uint	l2cewar0;	/* 0x20010 - L2 cache external write address register 0 */
	char	res2[4];
	uint	l2cewcr0;	/* 0x20018 - L2 cache external write control register 0 */
	char	res3[4];
	uint	l2cewar1;	/* 0x20020 - L2 cache external write address register 1 */
	char	res4[4];
	uint	l2cewcr1;	/* 0x20028 - L2 cache external write control register 1 */
	char	res5[4];
	uint	l2cewar2;	/* 0x20030 - L2 cache external write address register 2 */
	char	res6[4];
	uint	l2cewcr2;	/* 0x20038 - L2 cache external write control register 2 */
	char	res7[4];
	uint	l2cewar3;	/* 0x20040 - L2 cache external write address register 3 */
	char	res8[4];
	uint	l2cewcr3;	/* 0x20048 - L2 cache external write control register 3 */
	char	res9[180];
	uint	l2srbar0;	/* 0x20100 - L2 memory-mapped SRAM base address register 0 */
	char	res10[4];
	uint	l2srbar1;	/* 0x20108 - L2 memory-mapped SRAM base address register 1 */
	char	res11[3316];
	uint	l2errinjhi;	/* 0x20e00 - L2 error injection mask high register */
	uint	l2errinjlo;	/* 0x20e04 - L2 error injection mask low register */
	uint	l2errinjctl;	/* 0x20e08 - L2 error injection tag/ECC control register */
	char	res12[20];
	uint	l2captdatahi;	/* 0x20e20 - L2 error data high capture register */
	uint	l2captdatalo;	/* 0x20e24 - L2 error data low capture register */
	uint	l2captecc;	/* 0x20e28 - L2 error ECC capture register */
	char	res13[20];
	uint	l2errdet;	/* 0x20e40 - L2 error detect register */
	uint	l2errdis;	/* 0x20e44 - L2 error disable register */
	uint	l2errinten;	/* 0x20e48 - L2 error interrupt enable register */
	uint	l2errattr;	/* 0x20e4c - L2 error attributes capture register */
	uint	l2erraddr;	/* 0x20e50 - L2 error address capture register */
	char	res14[4];
	uint	l2errctl;	/* 0x20e58 - L2 error control register */
	char	res15[420];
} ccsr_l2cache_t;

/*
 * DMA Registers(0x2_1000-0x2_2000)
 */
typedef struct ccsr_dma {
	char	res1[256];
	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
	char	res2[4];
	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
	char	res3[4];
	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
	char	res4[8];
	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
	char	res5[4];
	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
	char	res6[56];
	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
	char	res7[4];
	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
	char	res8[4];
	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
	char	res9[8];
	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
	char	res10[4];
	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
	char	res11[56];
	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
	char	res12[4];
	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
	char	res13[4];
	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
	char	res14[8];
	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
	char	res15[4];
	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
	char	res16[56];
	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
	char	res17[4];
	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
	char	res18[4];
	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
	char	res19[8];
	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
	char	res20[4];
	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
	char	res21[56];
	uint	dgsr;		/* 0x21300 - DMA General Status Register */
	char	res22[11516];
} ccsr_dma_t;

/*
 * tsec1 tsec2: 24000-26000
 */
typedef struct ccsr_tsec {
	char	res1[16];
	uint	ievent;		/* 0x24010 - Interrupt Event Register */
	uint	imask;		/* 0x24014 - Interrupt Mask Register */
	uint	edis;		/* 0x24018 - Error Disabled Register */
	char	res2[4];
	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
	uint	minflr;		/* 0x24024 - Minimum Frame Length Register */
	uint	ptv;		/* 0x24028 - Pause Time Value Register */
	uint	dmactrl;	/* 0x2402c - DMA Control Register */
	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
	char	res3[88];
	uint	fifo_tx_thr;		/* 0x2408c - FIFO transmit threshold register */
	char	res4[8];
	uint	fifo_tx_starve;		/* 0x24098 - FIFO transmit starve register */
	uint	fifo_tx_starve_shutoff;		/* 0x2409c - FIFO transmit starve shutoff register */
	char	res5[96];
	uint	tctrl;		/* 0x24100 - Transmit Control Register */
	uint	tstat;		/* 0x24104 - Transmit Status Register */
	char	res6[4];
	uint	tbdlen;		/* 0x2410c - Transmit Buffer Descriptor Data Length Register */
	char	res7[16];
	uint	ctbptrh;	/* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
	uint	ctbptr;		/* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
	char	res8[88];
	uint	tbptrh;		/* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
	uint	tbptr;		/* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
	char	res9[120];
	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
	uint	tbase;		/* 0x24204 - Transmit Descriptor Base Address Register */
	char	res10[168];
	uint	ostbd;		/* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
	uint	ostbdp;		/* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
	uint	os32tbdp;	/* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
	uint	os32iptrh;	/* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
	uint	os32iptrl;	/* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
	uint	os32tbdr;	/* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
	uint	os32iil;	/* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
	char	res11[52];
	uint	rctrl;		/* 0x24300 - Receive Control Register */
	uint	rstat;		/* 0x24304 - Receive Status Register */
	char	res12[4];
	uint	rbdlen;		/* 0x2430c - RxBD Data Length Register */
	char	res13[16];
	uint	crbptrh;	/* 0x24320 - Current Receive Buffer Descriptor Pointer High */
	uint	crbptr;		/* 0x24324 - Current Receive Buffer Descriptor Pointer */
	char	res14[24];
	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
	uint	mrblr2r3;	/* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
	char	res15[56];
	uint	rbptrh;		/* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
	uint	rbptr;		/* 0x24384 - Receive Buffer Descriptor Pointer */
	uint	rbptrh1;	/* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
	uint	rbptrl1;	/* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
	uint	rbptrh2;	/* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
	uint	rbptrl2;	/* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
	uint	rbptrh3;	/* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
	uint	rbptrl3;	/* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
	char	res16[96];
	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
	uint	rbase;		/* 0x24404 - Receive Descriptor Base Address */
	uint	rbaseh1;	/* 0x24408 - Receive Descriptor Base Address High 1 */
	uint	rbasel1;	/* 0x2440c - Receive Descriptor Base Address Low 1 */
	uint	rbaseh2;	/* 0x24410 - Receive Descriptor Base Address High 2 */
	uint	rbasel2;	/* 0x24414 - Receive Descriptor Base Address Low 2 */
	uint	rbaseh3;	/* 0x24418 - Receive Descriptor Base Address High 3 */
	uint	rbasel3;	/* 0x2441c - Receive Descriptor Base Address Low 3 */
	char	res17[224];
	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
	uint	hafdup;		/* 0x2450c - Half Duplex Register */
	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
	char	res18[12];
	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
	uint	miimcom;	/* 0x24524 - MII Management Command Register */
	uint	miimadd;	/* 0x24528 - MII Management Address Register */
	uint	miimcon;	/* 0x2452c - MII Management Control Register */
	uint	miimstat;	/* 0x24530 - MII Management Status Register */
	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
	char	res19[4];
	uint	ifstat;		/* 0x2453c - Interface Status Register */
	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
	char	res20[312];
	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
	char	res21[4];
	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
	uint	car1;		/* 0x24730 - Carry Register One */
	uint	car2;		/* 0x24734 - Carry Register Two */
	uint	cam1;		/* 0x24738 - Carry Mask Register One */
	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
	char	res22[192];
	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
	char	res23[96];
	uint	gaddr0;		/* 0x24880 - Global address register 0 */
	uint	gaddr1;		/* 0x24884 - Global address register 1 */
	uint	gaddr2;		/* 0x24888 - Global address register 2 */
	uint	gaddr3;		/* 0x2488c - Global address register 3 */
	uint	gaddr4;		/* 0x24890 - Global address register 4 */
	uint	gaddr5;		/* 0x24894 - Global address register 5 */
	uint	gaddr6;		/* 0x24898 - Global address register 6 */
	uint	gaddr7;		/* 0x2489c - Global address register 7 */
	char	res24[96];
	uint	pmd0;		/* 0x24900 - Pattern Match Data Register */
	char	res25[4];
	uint	pmask0;		/* 0x24908 - Pattern Mask Register */
	char	res26[4];
	uint	pcntrl0;	/* 0x24910 - Pattern Match Control Register */
	char	res27[4];
	uint	pattrb0;	/* 0x24918 - Pattern Match Attributes Register */
	uint	pattrbeli0;	/* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd1;		/* 0x24920 - Pattern Match Data Register */
	char	res28[4];
	uint	pmask1;		/* 0x24928 - Pattern Mask Register */
	char	res29[4];
	uint	pcntrl1;	/* 0x24930 - Pattern Match Control Register */
	char	res30[4];
	uint	pattrb1;	/* 0x24938 - Pattern Match Attributes Register */
	uint	pattrbeli1;	/* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd2;		/* 0x24940 - Pattern Match Data Register */
	char	res31[4];
	uint	pmask2;		/* 0x24948 - Pattern Mask Register */
	char	res32[4];
	uint	pcntrl2;	/* 0x24950 - Pattern Match Control Register */
	char	res33[4];
	uint	pattrb2;	/* 0x24958 - Pattern Match Attributes Register */
	uint	pattrbeli2;	/* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd3;		/* 0x24960 - Pattern Match Data Register */
	char	res34[4];
	uint	pmask3;		/* 0x24968 - Pattern Mask Register */
	char	res35[4];
	uint	pcntrl3;	/* 0x24970 - Pattern Match Control Register */
	char	res36[4];
	uint	pattrb3;	/* 0x24978 - Pattern Match Attributes Register */
	uint	pattrbeli3;	/* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd4;		/* 0x24980 - Pattern Match Data Register */
	char	res37[4];